R&D Organization and Investment
In 2016 TSMC continued to invest in research and development, with total R&D expenditures amounting to 8% of revenue, a level that equals or exceeds the R&D investment of many other leading high- tech companies.
TSMC recognizes that the technology challenge of continuing to extend Moore’s Law, the doubling of semiconductor computing power every two years, is becoming increasingly complex and difficult. The efforts of the R&D organization are focused on enabling the Company to continuously offer its customers first-to-market, leading-edge technologies and design solutions that contribute to their product success in today’s competitive market environment. In 2016 the R&D organization met these challenges by completing the transfer to manufacturing of the industry leading 10nm technology, the 3rd generation of technology platform to make use of 3D FinFET transistors. The R&D organization continues to fuel the pipeline of technological innovation needed to maintain industry leadership. TSMC’s 7nm technology development is on track to meet the goal of production start-up in 2017. TSMC 5nm technology is now in the full development stage, and the definition and intensive early development efforts have been started for nodes beyond 5nm.
In addition to CMOS logic, TSMC conducts R&D on a wide range of other semiconductor technologies that provide the functionality customers require for mobile SoC and other applications. Highlights in 2016 include: the world’s first high-volume production of Integrated Fan-Out Package on Package (InFO PoP) for mobile application processor packaging; successful qualification of InFO PoP Gen-2 advanced packaging technology for mobile applications and InFO wafer-level fine-pitch fan-out technology for die-partition and high-speed applications; 0.18m second generation BCD (binary-coded decimal) technology resulting in the world’s highest performance quick charger and wireless charger in 2016; successful production launch of e-Flash 65nm/55nm node, NOR-based cell technologies, including 1-T cell and split-gate cell; completion of qualification of the 40nm node, split-gate cell technology for consumer electronics applications such as IoT and smartcards; and development and manufacturing qualification of 650V D-MISFET, 100V E-HEMT, and RF 30V D-MISFET GaN devices.
TSMC maintains a network of important external R&D partnerships and alliances with world-class research institutions, including IMEC, the highly regarded European R&D consortium, where TSMC is a core partner. TSMC also provides funding for nanotechnology research at leading universities worldwide to promote innovation and the advancement of nano-electronic technology. TSMC has established four joint research centers within Taiwan: National Taiwan University, National Chao Tung University, National Tsing Hua University, and National Cheng Kung University. The goal of these centers is to develop greater understanding of the devices and materials used in the manufacture of advanced silicon technologies.
R&D Accomplishments in 2016
● 10nm Technology
10nm technology offers substantial density improvement with better performance at same power or power reduction at the same chip performance compared to earlier technology generations and began customer product tape-out in the first quarter and production ramp-up in the fourth quarter of 2016.
● 7nm TechnologyTSMC focused on the manufacturing baseline process setup, yield learning, transistor and interconnect R/C performance improvement and the reliability evaluation of 7nm technology, which offers significant density improvement with better performance at same power or lower power consumption at comparable performance vs. 10nm technology. During the year, major customers and IP vendors completed IP design and started silicon validation. TSMC plans to complete 7nm qualification for risk production in 2017.
● 5nm Technology
Development activities in 2016 focused on test vehicle design and implementation, mask making, and pilot run. Even though the semiconductor industry is approaching the physical limits of silicon, 5nm technology still follows Moore’s Law and delivers substantial density improvement with better performance at same power or lower power consumption at comparable performance. TSMC will focus on manufacturing baseline process setup, yield learning, transistor and interconnect R/C performance improvement and reliability evaluation and plans to continue 5nm full development in 2017 and 2018 for risk production in 2019.
● Lithography Technology
The main focus for RD lithography in 2016 is 7nm and 5nm development. For 7 nm development, the primarily focus is on continuous improvement of overlay control, defect reduction, and patterning robustness in preparation for 7nm qualification. As for 5nm development, EUV lithography will be used to reduce the complex multiple-patterning process steps. In 2017, TSMC will take the delivery of newest generation of EUV scanners to meet the tightened overlay control and imaging requirement for 5nm and beyond.
In 2016, the EUV program made continuous improvement in light-source power and its stability, which has enabled faster learning rate and process development for advanced nodes. Additional progress was made with resist process, pellicle, and related mask blanks, as EUV technology moves closer to full scale R&D and manufacturing readiness.
● Mask Technology
Mask technology is an integral part of our advanced lithography. In 2016, R&D successfully completed the development of mask technology for the 7nm node. This technology is being transferred to the mask production organization. During the same period, solid progress was made on the development of mask technology for EUV lithography, including the reduction of native defects on mask blanks and the fabrication of EUV masks for lithographic processing of 7nm and 5nm nodes.
Integrated Interconnect and Packaging
CoWoS ®, InFO and Under-Bump-Metallurgy Free Integration (UBM-free integration, UFI) are part of the generic wafer level system integration (WLSI) technology platform, which leverages TSMC’s core competency in wafer processes for heterogeneous system integration and packaging to meet the specific customer needs in performance, power, profile, cycle time and cost. InFO, UFI and CoWoS ® are continuously evolving to fulfill diversified markets such as IoTs, automotive, high-performance computing and telecommunication.
● 3D IC
2016 was a landmark year for system integration, as TSMC launched the world’s first high-volume manufacturing (HVM) InFO PoP packaging for mobile applications processors. During the year, TSMC also successfully qualified InFO PoP Gen-2 advanced packaging technology for mobile applications and wafer-level fine-pitch InFO technology for die-partition and high-speed applications. Production ramp-up of fine-pitch fan-out HVM is expected in 2017. In interposer CoWoS ® technology, the application was rapidly extended to 16nm starting from the FPGA (field programmable gate array) family. In addition, TSMC leads the industry by starting mass production of super high-end accelerators that integrate multiple HBM2 (second generation high bandwidth memory) chips and GPUs, resulting in a brand new application for CoWoS ® in the HPC area of artificial intelligence and deep learning.
● Advanced Package
TSMC offers a wide variety of lead-free packaging solutions for mobile/handheld devices. 10nm FinFET Si with ultra-fine pitch copper packaging was developed and qualification was successfully completed in the fourth quarter of 2016. The low-cost and large die area up to 108 mm2 with highly reliable 80um pitch copper packaging technology will be inserted into customers’ mass production from 2017 onward. In 2016, the low-cost, innovative and highly reliable fan-in WLCSP technology was completed and transferred to Fab for mass production of die size 5x5mm2. Expanding its application envelope, in addition to larger die size 7x7mm2, this technology also passed the reliability qualification for even larger die sizes up to 10x10mm2.
● Advanced Interconnect
Several leading interconnect technologies were optimized and implemented in the 5nm node during 2016. Both chip performance and power utilization were effectively enhanced. These state-of-the-art technologies included an innovative integrated low-cost patterning process with the extension of immersion lithography and cutting-edge EUV patterning technology, optimized metal layer stacking combinations, and a novel thin copper barrier process with prominent reliabilities. In addition TSMC deployed experienced experts and relevant resources to develop technology nodes of 3nm and beyond.
Advanced Transistor Research
Innovation in transistor architectures and materials has enabled increased speed and reduction of power consumption in advanced logic technologies. TSMC is at the forefront of transistor research on devices with high mobility channel materials for beyond Silicon CMOS. Complementing this research are further efforts focusing on innovative solutions to address challenges to technology performance from parasitic resistances and capacitances. TSMC research is expected to pave the way for continued density scaling while maximizing performance and minimizing power on advanced logic technologies for mobile and high-performance applications.
TSMC offers a broad mix of technologies to address a wide range of applications:
● Mixed Signal/Radio Frequency (MS/RF) Technology
In 2016, TSMC developed a 7nm silicon, electromagnetic simulation-based design to facilitate high-speed circuit design with layout specifications. To meet growing demand for low-power consumption and leakage current in mobile devices, TSMC also introduced 16FF RF technology, e.g. for 4G LTE applications. In order to improve performance regarding insertion loss and isolation, TSMC further reduced the key parameter Ron-Coff to ~102 fs (femtoseconds) to enable cellular/Wi-Fi RF switch applications.
● Power IC/Bipolar-CMOS-DMOS (BCD) Technology
TSMC’s 0.18m second-generation BCD technology enabled the world’s highest-performance quick charger and wireless charger in 2016. 0.18µm third-generation BCD technology is ramping up and will provide an even better solution with higher performance at lower cost. Targeting 5V and below mobile power management, newly developed asymmetric power switch in 0.13µm BCD technology will enable higher efficiency power supply for mobile devices.
● Panel Drivers
TSMC completed process qualification of 40nm high-voltage 6V/25-32V low-power panel driver technology with several customer product verifications ongoing. This technology supports Super Retina display driver ICs and touch-display driver ICs for high-end mobile phones. In addition, TSMC introduced Phase-2 with a 22% SRAM bitcell reduction as well as 8V/25-32V process technology for OLED drivers; several customers have designs in and plan to tape out in the first quarter of 2017.
● Micro-electromechanical Systems (MEMS) Technology
In 2016, TSMC’s modular MEMS technology was qualified for mass production of accelerometers and a pilot run of high-resolution pressure sensors. Future plans include the development of next-generation high-sensitivity thin microphone, MEMS Si-pillar TSV (through silicon via) technology and BioMEMS applications.
● GaN Technology
In 2016, 650V D-MISFET, 100V E-HEMT, and RF 30V D-MISFET GaN devices were developed and qualified for manufacturing.
● Complementary Metal-Oxide-Semiconductor (CMOS) Image Sensor Technology
In 2016, CMOS image sensor technology made the following breakthroughs: (1) high-density wafer hybrid bond technology (2) second-generation wafer backside trench isolation for pixels and (3) composite metal grid structure for SNR (signal-to-noise ratio) per pixel improvement. The first breakthrough achieved the world’s most advanced pitch density. The second and third breakthroughs reduced per-pixel electrical and optical cross-talk for better image quality compared to previous generations of optical structures. All three technologies passed product and process qualification and are progressing toward mass production.
● Flash/Embedded Flash Technology
TSMC achieved several important milestones in embedded flash technologies in 2016. At the more mature 65nm/55nm node, NOR-based cell technologies, including 1-T cell and Split-Gate cell, were successfully put in production. At the 40nm node, split-gate cell technology completed qualification for consumer electronics applications such as IoT and smartcards, and also completed customer product qualification were put in production. This technology will be adopted for automobile electronics, the development is undergoing. Embedded flash development on the 28nm low-power and 28nm high-performance mobile computing platforms is underway for low-leakage applications in areas such as automobile electronics and micro controller units (MCU).
TSMC provides customers with advanced technology platforms that include the comprehensive design infrastructure required to optimize design productivity and cycle time. These include: design flows for electronic design automation (EDA); silicon-proven IP building blocks, such as libraries; and simulation and verification design kits, i.e., process design kits (PDK) and technology files.
The availability of 7nm FinFET saw improvements in design infrastructure using an advanced CPU core as the vehicle to support customers’ adoption of 7nm FinFET. (EDA tool certification results can be found on TSMC-Online.) TSMC also extended its IP quality program (TSMC 9000) to allow IP audits to be performed either at TSMC or at TSMC-certified laboratories. To help customers plan new product tape-outs incorporating IP/Library from TSMC’s Open Innovation Platform ® (OIP) ecosystem, the OIP ecosystem added a portal to connect customers to an ecosystem of 43 solution providers.
TSMC’s technology platforms provide a solid foundation to facilitate the design process. Customers can design directly using the Company’s internally developed IP and tools or using those that are available from TSMC’s OIP partners.
Tech Files and PDKs
TSMC provides a broad range of process design kits (PDKs) for digital logic, mixed-signal, radio frequency (RF), high-voltage driver, CMOS image sensor (CIS) and embedded flash technologies across a range of technology nodes from 0.5µm to 7nm. In addition, the Company provides technology files for DRC (design rule checking), LVS (layout verification of schematic), RC (resistance-capacitance) extraction, automatic place and route, and a layout editor to ensure process technology information is accurately represented in EDA (electronic design automation) tools. By 2016, TSMC had provided more than 8,200 technology files and more than 270 PDKs via TSMC-Online. There are more than 100,000 customer downloads of these files every year.
Library and IP
TSMC and its alliance partners offer customers a rich portfolio of reusable IPs, which are essential building blocks for many circuit designs. In 2016, over 60% of new tape-outs at TSMC adopted one or more libraries or IP from TSMC and/or OIP partners, as the Company expanded its library and silicon IP portfolio to contain more than 12,000 items, a 20% increase over 2015.
Design Methodology and Flow
In 2016 TSMC addressed critical design challenges associated with the new 7nm FinFET technology for digital and SoC applications by announcing the readiness of reference flows through OIP collaboration that feature FinFET-specific design solutions and methodologies for performance, power and area optimization.
A strong portfolio of intellectual property rights strengthens TSMC’s technology leadership and protects our advanced and leading edge technologies. In 2016, TSMC received a total of 2,294 U.S. patents, which is a 30% increase from the previous year, and thus reached a historical-high ranking of #9 in terms of U.S. patent grants. Additionally, TSMC received over 1,200 issued patents in Taiwan and PRC, which is a 59% increase from the previous year, as well as patents in other various countries. TSMC’s patent portfolio now reaches over 35,000 patents worldwide (including patent applications in queue). We continue to implement a unified strategic plan for TSMC’s intellectual capital management. Strategic considerations and close alignment with the business objectives drive the timely creation, management and use of our intellectual property.
At TSMC, we have built a process to extract value from our intellectual property by aligning our intellectual property strategy with our R&D, operations, business objectives, marketing, and corporate development strategies. Intellectual property rights protect our freedom to operate, enhance our competitive position, and give us leverage to participate in many profit-generating activities.
We have worked continuously to improve the quality of our intellectual property portfolio and to reduce the costs of maintaining it. We plan to continue investing in our intellectual property portfolio and intellectual property management system to ensure that we protect our technology leadership and receive maximum business value from our intellectual property rights.
TSMC University Collaboration Programs
In recent years, TSMC has significantly expanded its interaction with universities in Taiwan with the collaboration of research projects at some of the nation’s most prestigious institutions. The mission of these projects is twofold: to increase the number of highly qualified students suitable for employment in semiconductor industry, and to inspire university professors to initiate research programs that focus on the frontiers of semiconductor science, including device, process and materials technology, semiconductor manufacturing and engineering science, and specialty technologies for electronic applications. Since 2013, TSMC has established four research centers at National Taiwan University, National Chiao Tung University, National Cheng Kung University and National Tsing Hua University. In 2015, TSMC started cooperation with International College of the Semiconductor Technology and continued to enhance cooperation with other schools. Currently, several hundred high-caliber students have joined the research centers with backgrounds in the disciplines of electronics, physics, materials engineering, chemistry, chemical engineering and mechanical engineering.
In addition, TSMC also conducts strategic research projects at top overseas universities, such as Stanford, MIT, UC Berkeley and so on. The focus is on disruptive capabilities in transistors, interconnect, patterning, modeling and special technologies.
TSMC University Shuttle Program
The TSMC University Shuttle Program was established to provide professors at leading research universities worldwide with access to the advanced silicon process technologies needed to research and develop innovative circuit design concepts. This program links motivated professors and graduate students to enthusiastic managers at TSMC with the goals of promoting excellence in the development of advanced silicon design technologies and nurturing new generations of engineering talent in the semiconductor field.
The program provides access to TSMC silicon process technologies for digital, analog/mixed-signal circuits, RF designs and micro-electromechanical system designs. Participants in the TSMC University Shuttle Program include major university research groups worldwide. TSMC and the University Shuttle Program participants achieve “win-win” collaboration through the program, which allows graduate students to implement exciting designs and achieve silicon proof points for innovations in various end-applications.
To maintain and strengthen TSMC’s technology leadership, the Company plans to continue investing heavily in R&D. In addition to 7nm and 5nm CMOS nodes already in the pipeline, the Company’s reinforced exploratory R&D work is on track to establish a solid foundation to feed into technology platforms beyond the 5nm node. The Company’s exploratory work focuses on new transistors and technologies, such as 3D structures, strain-engineered CMOS, high-mobility materials and novel 3D IC devices. These studies emphasize innovation and are guided by deep understanding of the fundamental physics of nanometer CMOS transistors and related technologies. The Company also continues to collaborate with external research bodies from academia and industry consortia alike with the goal of extending Moore’s Law and paving the road to future cost-effective technologies and manufacturing solutions for its customers.
With a highly competent and dedicated R&D team and its unwavering commitment to innovation, TSMC is confident in its ability to deliver the best and most cost-effective SoC technologies to its customers and to drive future business growth and profitability for years to come.
Summary of TSMC's Major Future R&D Projects
7nm logic platform technology and applications
4th generation FinFET CMOS platform technology for SoC
5nm logic platform technology and applications
5th generation FinFET CMOS platform technology for SoC
Cost-effective solution with better form factor and performance for System-in-Package (SiP)
2016 ~ 2017
EUV lithography and related patterning technology to extend Moore’s Law
2016 ~ 2019
Specialty SoC technology (including new NVM, MEMS, RF, analog) and transistors for 5nm node and beyond
2015 ~ 2019
The projects above account for roughly 70% of the total R&D budget for 2017, estimated to be around 8% of 2017 revenue.