R&D Organization and Investment
In 2015, TSMC continued to invest in research and development, with total R&D expenditure amounting to 8% of revenue, a level that equals or exceeds the R&D investment of many other high-tech leaders.
TSMC recognizes that the technology challenge of continuing to extend Moore’s Law, the doubling of semiconductor computing power every two years, is becoming increasingly complex. The efforts of the R&D organization are focused on enabling the Company to continuously offer its customers first-to-market, leading-edge technologies and design solutions that contribute to their product success in today’s challenging market environment. In 2015 the R&D organization met these challenges by completing transfer to manufacturing of the industry leading 16FF+ technology, the first integrated technology platform to make use of 3D FinFET transistors. The R&D organization continues to fuel the pipeline of technological innovation needed to maintain leadership. TSMC’s 10nm technology development is on track to meet the goal of production start-up in 2016. TSMC 7nm technology is now in the full development stage, while the 5nm node is under definition and subject to intensive early development efforts.
In addition to CMOS logic, TSMC conducts R&D on a wide range of other semiconductor technologies that provide the functionality customers require for mobile SoC and other applications. Highlights achieved in 2015 include: Chip-On-Wafer-On-Substrate (CoWoS® ) technology enhancement to include areas exceeding
1000mm2 in size; full qualification of 3D InFO technology qualification and transfer to manufacturing; Through-Silicon Via (TSV) packaging ramp-up to high volume; development of 0.13µm Bipolar-CMOS-DMOS (BCD) technology for manufacture on 12-inch wafers; the addition of RF capability for 55nm e-Flash technology aimed at IoT applications; qualification for manufacture of a 650V GaN High-Electron-Mobility Transistor (HEMT); and qualification of the 55nm high-voltage process for display drivers.
TSMC maintains a network of important external R&D partnerships and alliances with world-class research institutions, such as IMEC, the well-respected European R&D consortium, where TSMC is a core partner. TSMC also provides funding for nanotechnology research at leading universities worldwide to promote innovation and the advancement of nano-electronic technology. TSMC has established four joint research centers within Taiwan to include National Taiwan University, National Chao Tung University, National Tsing Hua University, and National Cheng Kung University. The goal of these centers is to develop greater understanding of the devices and materials used in the manufacture of advanced Si technologies.
R&D Accomplishments in 2015
● 10nm Technology
10nm technology will offer substantial power reduction for the same chip performance compared to earlier technology generations. Development activities in 2015 focused on manufacturing baseline process setup, design rule fix, yield learning, transistor performance improvement, and process/product reliability evaluation. Key customers and IP vendors have verified their IP with 10nm technology. 10nm technology began customer product tape-out in the first quarter of 2016.
● 7nm Technology
7nm technology offers substantial density improvement and power reduction with the same chip performance as 10nm technology. Development activities in 2015 focused on manufacturing baseline process setup, yield learning, transistor and interconnect R/C performance improvement and reliability evaluation. TSMC plans to continue 7nm full development in 2016 for risk production in 2017.
The main focus for RD lithography in 2015 is 10nm and 7nm development. For 10nm development, the primarily focus is on continuous improvement of overlay control and patterning robustness in preparation for 10nm qualification. As for the 7nm development, new resist material and advanced mask technology were optimized to provide additional patterning enhancement and design rule shrinkage with immersion process. Furthermore, TSMC will take the delivery of newest generation of immersion scanner to meet the tighten overlay control and imaging requirement for 7nm and beyond.
In 2015, the EUV program has made significant improvement in laser power and its stability. The stability and improvement in source power has enabled faster learning rate and process development for advanced nodes. In addition, EUV resist process, pellicle, and related mask blank have all made significant progress. The EUV technology is stepping closer to full scale RD and manufacturing readiness for advanced nodes.
● Mask Technology
Mask technology is an integral part of our advanced lithography. In 2015, R&D successfully completed the development of mask technology for the 10nm node. This technology is being transferred to the mask production organization. During the same period, solid progress was made on the development of mask technology for EUV lithography, including the reduction of native defects on mask blanks and the fabrication of EUV masks for lithographic processing of sub-10nm nodes.
Integrated Interconnect and Packaging
● 3D IC
In 2015, TSMC successfully qualified InFO PoP advanced packaging technology, with a non-TSV, low-cost solution for mobile customers. High Volume Manufacturing (HVM) production ramp is expected in 2016. The CoWoS® technology continues to expand its application from Field-Programmable Gate Array (FPGA) to network and to high-performance computing; the interposer size also expands to larger than reticle dimension by CoWoS-XL technology.
● Advanced Package Development
TSMC offers a wide variety of lead-free packaging solutions for mobile/handheld devices. In 2015, 10nm FinFET Si with ultra-fine pitch copper bump Bump-on-Trace (BoT) packaging was under development. It is expected to complete the package qualification in the second quarter of 2016. In 2015, a low-cost, innovative and highly reliable 2-mask UBM-Free Integration (UFI) fan-in WLCSP technology is in mass production for die size 5x5mm2, and passed qualification for larger die sizes up to 7x7mm2.
● Advanced Interconnect
Development of low-resistance Cu and low-capacitance dielectric continued to be the primary focus in 2015. At the 7nm node, a new patterning process and a novel dielectric scheme have been developed to shrink line width/space and reduce the capacitance between copper lines. A low damage low-k was delivered to reduce capacitance impact. For the 5nm node and beyond, TSMC developed a design-friendly advanced line patterning scheme and processes that allow copper line width and spacing to be further reduced. A new multi-via patterning process was employed to further improve CD uniformity. A low-resistivity metal scheme with ultra-thin barrier was demonstrated with excellent reliability performance.
Advanced Transistor Research
Innovation in transistor architectures and materials has enabled increased speed and reduction of power consumption in advanced logic technologies. TSMC is at the fore-front of transistor research with a focus on devices with high mobility channel materials, such as germanium and III-V compound semiconductors. The Company’s track record in both p- and n- channel germanium transistors, including record-breaking device performance, was highlighted at the 2015 International Electron Device Meeting (IEDM).
TSMC offers a broad mix of technologies to address a wide range of applications:
● Mixed Signal/Radio Frequency (MS/RF) Technology
In 2015, TSMC developed a 10nm silicon and EM simulation-based LC-tank design solution to facilitate high-speed SerDes circuit design with various options of metal scheme and layout specifications to shorten design turnaround time. TSMC also offered the IPD-II solution for high-Q (Q>30 @700MHz) inductor and high-precision thin-film resistor for 4G LTE application. In order to achieve better performance in insertion loss and isolation, TSMC further reduced the key parameter Ron-Coff to ~130 fs in 0.18µm SOI process to enable cellar/Wi-Fi RF switch applications as lower-cost alternatives replacing traditional compound semiconductor-based solutions.
● Power IC/BCD Technology
The third generation of 0.18µm BCD technology adopted TSMC proprietary device structure, which increased world-leading performance with an even lower cost. With this technology, mobile power management ICs can meet the increasing power demand of mobile devices with higher-power efficiency.
● Panel Drivers
40nm high-voltage low-power process technology was readied for production with plans to complete qualification by the first quarter of 2016. This technology supports Super Retina display driver IC and touch-display driver integration IC for high-end mobile phones. This process was made available for customer tape-outs also in the first quarter of 2016.
● Micro-electromechanical Systems (MEMS) Technology
In 2015, TSMC’s modular MEMS technology was qualified for mass production of accelerometers and a pilot run of high-resolution pressure sensors. Future plans include development of next-generation high-sensitivity thin microphone, MEMS Si-pillar TSV technology, and BioMEMS applications.
● GaN Technology
TSMC is the first and only company to offer both 100V and 650V GaN foundry service in a 6-inch fab. In 2015, the R&D team completed 650V E-HEMT development and qualified for manufacture a high electron mobility transistor configuration for high-power, high-frequency applications with low Ron (resistance when on) and high-breakdown voltage.
● Flash/Embedded Flash Technology
TSMC achieved several important milestones in embedded flash technologies in 2015. At the more mature 65nm/55nm node, NOR-based cell technologies, including 1-T cell and Split-Gate cell, were successfully put in production. At the 40nm node, split-gate cell technology completed qualification for consumer electronics applications such as IoT and smartcards and is now undergoing customer product qualification. Embedded flash development on the 28nm low-power and 28nm high-performance mobile computing platforms is underway for low-leakage applications in areas such as automobile electronics and micro controller units (MCU).
TSMC provides customers with advanced technology platforms that include the comprehensive design infrastructure required to optimize design productivity and cycle time. These include: design flows for electronic design automation (EDA); silicon-proven IP building blocks, such as libraries; and simulation and verification design kits, i.e., process design kits (PDK) and technology files.
The availability of 10FF saw improvements in design infrastructure using an advanced CPU core as the vehicle to support customers’ adoption of 10nm FinFET (EDA tool certification results can be found on TSMC-Online.). TSMC also extended its IP quality program (TSMC9000) to allow IP audits to be performed either at TSMC or at TSMC-certified laboratories. To help customers plan new product tape-outs incorporating IP/Library from TSMC Open Innovation Platform® (OIP) ecosystem, the OIP ecosystem added a portal to connect customers to an ecosystem of 43 solution providers.
TSMC’s technology platforms provide a solid foundation for design enablement. Customers can design directly using the Company’s internally developed IP and tools or using those that are available via our OIP partners.
Tech Files and PDKs
TSMC provides a broad range of process design kits (PDKs) for digital logic, mixed-signal, radio frequency (RF), high-voltage driver, CMOS Image Sensor (CIS) and embedded flash technologies across a range of technology nodes from 0.5µm to 10nm. In addition, the Company provides technology files for DRC, LVS, RC extraction, automatic place and route, and a layout editor to ensure process technology information is accurately represented in EDA tools. By 2015, TSMC had provided more than 7,500 technology files and more than 200 PDKs via TSMC-Online. There are more than 100,000 customer downloads of these files every year.
Library and IP
TSMC and its alliance partners offer our customers a rich portfolio of reusable IP, which are essential building blocks for many circuit designs. In 2015, over 60% of new tape-outs at TSMC adopted one or more libraries or IP from TSMC and/or our IP partners, as the Company expanded its library and silicon IP portfolio to contain more than 10,000 items, an 18% increase over 2014.
Design Methodology and Flow
In 2015, TSMC addressed critical design challenges associated with the new 10nm FinFET technology for digital and SoC applications by announcing the readiness of reference flows through OIP collaboration that feature FinFET-specific design solutions and methodologies for performance, power and area optimization.
A strong portfolio of intellectual property rights strengthens TSMC’s technology leadership and protects our advanced and leading edge technologies. In 2015, TSMC received a record breaking 1,768 U.S. patents, as well as 779 issued patents in Taiwan and the PRC, and other patents issued in various other countries. In 2015, TSMC ranked #23 in the “Top 50” U.S. patent grants. TSMC’s patent portfolio now reaches almost 30,000 patents worldwide (including patent applications in queue). We continue to implement a unified strategic plan for TSMC’s intellectual capital management. Strategic considerations and close alignment with the business objectives drive the timely creation, management and use of our intellectual property.
At TSMC, we have built a process to extract value from our intellectual property by aligning our intellectual property strategy with our R&D, operations, business objectives, marketing, and corporate development strategies. Intellectual property rights protect our freedom to operate, enhance our competitive position, and give us leverage to participate in many profit-generating activities.
We have worked continuously to improve the quality of our intellectual property portfolio and to reduce the costs of maintaining it. We plan to continue investing in our intellectual property portfolio and intellectual property management system to ensure that we protect our technology leadership and receive maximum business value from our intellectual property rights.
TSMC University Collaboration Programs
In recent years, TSMC has significantly expanded its interaction with universities in Taiwan with the establishment of four research centers located at the nation’s most prestigious universities. The mission of these centers is twofold: to increase the number of highly qualified students suitable for employment in semiconductor industry, and to inspire university professors to initiate research programs that focus on the frontiers of semiconductor science, including device, process and materials technology, semiconductor manufacturing and engineering science, and specialty technologies for electronic applications. TSMC continues to expand and enhance the research portfolio at the four research centers at National Taiwan University, National Chiao Tung University, National Cheng Kung University and National Tsing Hua University. In 2015, several hundred more high-caliber students joined the research centers with backgrounds representing the disciplines of electronics, physics, materials engineering, chemistry, chemical engineering and mechanical engineering.
In addition, TSMC also conducts strategic research projects at top overseas universities, such as Stanford, MIT, UC Berkeley, etc. The focus is on disruptive capabilities in transistors, interconnect, patterning, modeling and special technologies.
TSMC University Shuttle Program
The TSMC University Shuttle Program was established to provide professors at leading research universities worldwide with access to the advanced silicon process technologies needed to research and develop innovative circuit design concepts. This program links motivated professors and graduate students to enthusiastic managers at TSMC with the goals of promoting excellence in the development of advanced silicon design technologies and nurturing new generations of engineering talent in the semiconductor field.
The program provides access to TSMC silicon process technologies for digital, analog/mixed-signal circuits, RF designs and micro-electromechanical system designs. Participants in the TSMC University Shuttle Program include major university research groups worldwide. TSMC and the University Shuttle Program participants achieve “win-win” collaboration through the program, which allows graduate students to implement exciting designs and achieve silicon proof points for innovations in various end-applications.
To maintain and strengthen TSMC’s technology leadership, the Company plans to continue investing heavily in R&D. In addition to 10nm and 7nm CMOS nodes in the pipeline, the Company’s reinforced exploratory R&D work is on track to establish a solid foundation to feed into technology platforms beyond the 7nm node. The Company’s exploratory work focuses on new transistors and technologies, such as 3D structures, strained-layer CMOS, high-mobility materials and novel 3D IC devices. These studies emphasize innovation and are guided by deep understanding of fundamental physics of nanometer CMOS transistors and related technologies. The Company also continues to collaborate with external research bodies from academia and industry consortia alike with the goal of extending Moore’s Law and paving the road to future cost-effective technologies and manufacturing solutions for its customers.
With a highly competent and dedicated R&D team and its unwavering commitment to innovation, TSMC is confident in its ability to deliver the best and most cost-effective SoC technologies to its customers and to drive future business growth and profitability for years to come.
Summary of TSMC’s Major Future R&D Projects
110nm logic platform technology and applications
3rd generation FinFET CMOS platform technology for SoC
7nm logic platform technology and applications
4th generation FinFET CMOS platform technology for SoC
Cost-effective solution with better form factor and
2016 ~ 2017
EUV and multiple e-beam to extend Moore’s Law
2016 ~ 2019
Specialty SoC technology (including new NVM, MEMS, RF,
2015 ~ 2019
The projects above accounted for roughly 70% of the total R&D budget in 2016, estimated to be around 8% of 2016 revenue.