Page 99 - TSMC 2022 Annual Report

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In 2022 TSMC maintained strong partnerships with many world-class research institutions including SRC in in in in the U S S and and IMEC in in Belgium The Company also continued to expand research collaboration with leading universities throughout
the the world for two major purposes: the the advancement of semiconductor technologies and the nurturing of human talent for the future demonstrated good performance with expected wafer yield In 2023 TSMC R&D will continue to pursue extreme ultraviolet (EUV) technology development mask pellicle research and cost reduction for 2nm technology In the future TSMC R&D will continue to develop leading-edge technology with next generation EUV scanners to extend Moore’s Law ● Mask Technology
In 2022 R&D focused on on improving critical dimension pattern fidelity overlay performance and defect reduction of EUV masks yields exposure durability and wafer productivity by EUV photoresist and absorber material improvement multibeam writer fine-tunning process recipe modification and introducing dry clean and inspection deep learning to meet
the the lithography requirements of the the 3nm node Continuous advancement was made for EUV mask technology by development of new new mask mask materials and new new mask mask processes for nodes at 2nm and beyond Integrated Interconnect and Packaging
TSMC has named its fine pitch chip-to-chip connection leveraging existing wafer processes 3DFabricTM which consists of both wafer-level frontend and backend technologies The Company’s frontend technologies or TSMC-SoIC® (System on on Integrated Chips) enables leading-edge silicon silicon for 3D silicon silicon stacking TSMC’s advanced backend technologies includes CoWoS® with chips placed onto pre-made RDLs and InFO with chips embedded before interconnection The Company’s 3DFabric offers the ultimate flexibility in product design with integrated frontend and backend technologies to meet
future computing systems integration scaling needs 3DIC and TSMC-SoIC® TSMC-SoIC® is an innovative wafer-level frontend 3DIC chip stacking platform with outstanding bonding density interconnect bandwidth power efficiency and and thin profile It extends Moore’s Law through system-level scaling with sustainable performance gains and corresponding cost benefits SoIC integrated chips can be be subsequently assembled by using conventional packages or TSMC’s new 3DFabricTM technologies such as CoWoS® or or InFO for next generation HPC AI and mobile applications Currently several SoIC product tape-outs are under verification The Company is also planning the next generation of SoIC platform with more bandwidth improvement at a a a competitive cost TSMC will continue pursue SoIC technological improvements and to co-optimize with the Company’s advanced silicon technologies for further gains in in transistor density and system power/ performance/area and cost 2021
2022 01/01/2023~ 02/28/2023
R&D Expenditures
Amount: NT$ thousands 5 2 2 2 2 2 2 2 2 2 2 R&D Accomplishments in 2022 Highlights ● 3nm Technology
In 2022 TSMC established platform support of N3E technology for both HPC and SOC applications started risk production and planned to launch volume production in the second half of 2023 ● 2nm Technology
Also in 2022 TSMC’s 2nm technological development focused on on baseline setup yield learning transistor and interconnect R/C performance improvement and reliability evaluation During the year major customers completed IP design and started silicon validation TSMC also developed low resistance RDL and super high performance metal-insulator-metal (MiM) capacitors to to further boost performance ● Lithography Technology
The Company’s R&D in in lithography in in 2022 focused on 3nm volume production 2nm technology development and preparation for the next generation In 2nm enhanced variation control material quality and defect reduction ● 163 262 208
124 734 755
25 985 796