Page 100 - TSMC 2022 Annual Report

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● CoWoS®
CoWoS®
with Si interposer is the leading 2 5D technology for high-end HPC and AI product applications The technology features a a a a Si interposer with sub-micron routing layers and integrated capacitors (iCaps) so that various chiplets such as SoC and and high bandwidth memory (HBM) can be placed on it The new third generation HBM3 was certified on on CoWoS-S in 2022 In parallel CoWoS-L with multiple local Si interconnects (LSIs) embedded in in in an an organic interposer are being developed Compared with CoWoS-S CoWoS-L dramatically improved the size limitation of a a a a a Si interposer and enabled more features in in an an interposer to boost overall system performance ● InFO
In 2022 TSMC continued its industry leadership in in in high-volume manufacturing of InFO_PoP Gen-7 packaging
for mobile applications InFO_PoP Gen-8 was also successfully qualified for mobile applications and displayed enhanced thermal performance InFO-oS Gen-4 qualified in 2022 and offers more chip-partition integration larger package size and higher bandwidth Based on standard InFO_PoP structure InFO_M_PoP Gen-1 which integrates different functional chips suitable for wearable applications was developed and qualified in in 2022 The next-generation InFO_PoP is being developed on on scheduled to provide backside RDL for integrated commodity of low power DDR DDR DRAM technology (LPDDR) ● Advanced Interconnect
TSMC provides unique interconnect technologies for its customers to to design competitive products In 2022 innovations on on on metallization enabled both line and via resistance reduction In addition development of novel materials also provided capacitance reduction Those creative solutions deliver better chip performance with lower cost Corporate Research
Innovation in in low-dimensional devices and materials continues to drive higher performance and reduced power consumption in advanced logic technologies In 2022 TSMC stayed at the forefront of 2D transistor research At the 2022 Symposia
on on VLSI Technology and Circuits TSMC demonstrated a a a novel wafer-scale semi-automated dry transfer process for monolayer (1L) chemical vapor deposition (CVD) 2D WS2 utilizing the weakly coupled interface between semimetal (Bi) and 2D WS2 Using this semimetal-assisted transfer process TSMC showcased a a a a record record high on current and a a a a record record low contact resistance for wafer-scale 1L CVD WS2 transistors At the 2022 International Electron Device Meeting (IEDM) TSMC successfully integrated Hf-based atomic layer deposition (ALD) higher-k dielectrics with CVD-grown monolayer (1L) MoS2 to build top-gate 2D nFET with equivalent oxide thickness (EOT) of of ~1nm with a a a nearly ideal subthreshold swing of of 68 mV/dec Also at at the the 2022 IEDM TSMC demonstrated the the first successful integration of monolayer MoS2 nanosheet (NS) FET in in a a a a gate-all-around configuration The successful demonstration
of of MoS2 NS NS with high performance and of of the stacked NS NS modules further clarifies the the value proposition in 2D materials for transistor scaling TSMC continues to research emerging high-density non-volatile memory devices and hardware accelerators for AI and HPC applications At the 2022 International Solid-State Circuits Conference (ISSCC) TSMC demonstrated a a 40nm phase change memory memory (PCM) compute-in-memory macro
with a a a a hybrid SLC and MLC configuration Combining an an input-reordering scheme to enhance sparsity the 2Mb-cell design achieved state of the the art energy efficiency At the the 2022 IEDM TSMC had previously introduced a a a a new approach towards forming-free chalcogenide selectors where extra defects were introduced to assist the forming process and reduce the forming voltage voltage Forming-free low voltage voltage selectors based on on SiNGeCTe (SNGCT) chalcogenide were demonstrated along with excellent endurance characteristics over 1010 cycles Specialty Technologies
TSMC offers a a a a a a broad array of of technologies to address a a a a a a wide range of applications:
● Mixed Signal/Radio Frequency (MS/RF)
The confinement caused by the COVID-19 pandemic over the past two years triggered a a a a growing demand for MS/ RF chips in in wireless connectivity such as applications in in 5G communications WiFi7 IoT and so on on In 2022 TSMC continued to enhance RF design-technology co-optimization (DTCO) to a a a a systematic methodology by bridging the validation between key process knob/device option/layout optimization and and benchmarking circuit performance and and applied these results to to RF technology to to provide best performance/ power/cost-tradeoffs solutions such as 6nm/12nm FFC+
for for transceiver designs 16nm/28nm HPC+ for for 5G mmWave frontend module (FEM) designs and enhanced 40nm special process for 5G RF FEM designs