Page 75 - TSMC 2019 Annual Report

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Lithography Technology through-silicon-via (TSV) to enable the most advanced 3D IC technologies Currently TSMC has accomplished the process validation for TSMC-SoIC® and developed micron-level bonding- pitch processes with promising electrical yield and reliability data This shows TSMC’s readiness and the capability of TSMC- SoIC®-based production for any potential customers In brief the the TSMC-SoIC® technology provides the the opportunity not
only to to sustain Moore’s Law but also to to achieve a a a a a a significant breakthrough in SoC performance 73
Advanced Fan-Out Fan-Out and InFO (Integrated Fan-Out)
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In 2019 TSMC continued to lead in in in high-volume manufacturing of InFO-PoP Gen-4 packaging for mobile applications processors and Integrated Fan-Out on Substrate (InFO_oS) HPC chip partition applications InFO-PoP Gen-5 and InFO_oS Gen-2 were also successfully qualified for mobile and HPC applications respectively InFO-PoP Gen-5 qualification meant a a a a a smaller package size with more pin counts and better power integrity InFO_oS Gen-2 provided more chip partition integration with larger package size and and higher bandwidth Continuous development of multi-die heterogeneous integration with finer- pitch die-to-die interconnection has led to to new InFO without substrate for consumer applications New generation IPD (integrated passive device) technology which provides higher density capacitors and low ESL (effective series inductance)
for for electrical performance boost passed qualification on on InFO-PoP InFO-PoP This enhanced InFO-PoP InFO-PoP will benefit both AI and 5G mobile applications New high volume manufacturing of IPD is scheduled to begin in in 2020 The focus for R&D lithography in 2019 was on 5nm technology transfer 3nm technology development and preparation of 2nm to move beyond development 5nm technology was smoothly transferred and R&D is working with the the fab to resolve the the remaining EUV EUV production issues As for 3nm development EUV EUV (extreme ultraviolet) lithography showed promising imaging capability with expected wafer yield R&D is working on EUV to reduce mask defects in in scanner and overlay errors while lowering overall cost In 2020 TSMC will focus intensely on improving EUV quality and and cost in 2nm technology and and beyond In 2019 the Company’s EUV program made continuous improvement in in light-source power and stability enabling faster learning rates and process development for advanced nodes Additional progress was made with resist process pellicle and related mask blanks as as EUV moves closer to full scale manufacturing readiness •
M a s k T e c h n o o l o o g y Mask technology is an an integral part of advanced lithography In 2019 R&D successfully completed 5nm node mask technology transfer and and smoothly implemented more complicated and and advanced EUV mask technology in 3nm node Solid progress was made on on on production yield cycle time and the reduction of blank defects to meet high-volume manufacturing requirements Integrated Interconnect and Packaging
TSMC has pushed the system performance envelope beyond Moore’s Law by continuously upgrading wafer level system integration (WLSI) technologies in in in both interconnect pitch density and system sizes WLSI encompasses innovative technologies with frontend 3D integration system-on- integrated-chip (TSMC-SoIC®) and backend 3D integration including Integrated Fan-Out (InFO) and Chip on on Wafer on on Substrate (CoWoS®) Armed with TSMC’s most advanced node wafers/chips and and and mix-and-match frontend 3D 3D and and and backend 3D 3D system integration customers can build differentiated products on TSMC’s unique wafer-to-package turnkey services Demand for CoWoS® remained strong throughout 2019 as a a a a result of rapid growth in the HPC and AI markets The unique requirements for this product category include the integration of logic chips with the most computing power and memory chips with greatest capacity and and bandwidth – exactly where CoWoS® excels To meet the increasing production demand advanced backend fabs AP3 and AP5 joined forces with AP1 the original CoWoS® CoWoS® fab to provide the needed CoWoS® CoWoS® capacity for our customers On the technology front CoWoS® Gen-4 was developed to further boost overall performance at the the package level by expanding the Si interposer dimensions The CoWoS® Gen-4 features an interposer area up to 1 700 mm2 which is large enough to accommodate one full-reticle size SoC chip and and up to six 3D high bandwidth memory (HBM) stacks CoWoS® Gen-5 with an interposer area up to 2 2 400 mm2 is currently being developed with new chip architectures in in in mind such as chiplets TSMC-SoIC® and HBM3 (third generation high bandwidth memory) •
3D IC IC and TSMC-SoIC® (System-on-Integrated Chips)
System-on-Integrated Chips (TSMC-SoIC®) is an innovative wafer-level package technology that can holistically integrate multiple chiplets into a a a single SoC chip chip with a a a smaller footprint and thinner profile Through this technology advanced SoC chips (made by 7nm 5nm or even 3nm nodes) can be integrated with multi-tier multi-functional chips for the embodiment of high high high speed high high high bandwidth low power high high high pitch density and minimal footprint heterogeneous 3D IC integration Unlike conventional package technology TSMC-SoIC® applies an essential copper-to-copper bonding structure along with •
Si Interposer and CoWoS® (Chip on on Wafer on on Substrate)