Technology Leadership

R&D Organization and Investment

TSMC further expanded many aspects of Research and Development in 2012 to strengthen Technology Leadership. In 2012, the total R&D budget was 8.0% of total revenue. This level of R&D investment equals or exceeds that of many leading-edge technology companies. Along with the budget increase, the R&D organization increased staffing by over 27.5%.

TSMC recognizes that the technology challenge required to extend Moore's Law, the business law behind CMOS scaling, is getting increasingly complex. R&D Vice Presidents bring their rich industry experiences to lead the strengthening of the R&D team and to navigate through the technological and competitive challenges ahead. In 2012, TSMC worked intensively on ramping 28nm technology, which contributed close to 22% of fourth quarter 2012 revenue and will further increase in 2013.

TSMC accelerated the development of advanced transistors, especially 3D transistors using FinFET structure for 16nm process node, embedded memories, and copper (Cu)/low-K interconnect technologies. During 2012, the R&D organization once again proved its capabilities by developing 20nm technology as well as establishing 16nm transistor leadership capabilities. Furthermore, TSMC broadened the horizon of transistor research by investing R&D in alternative high-speed and low-power channel materials other than silicon, such as germanium and III-V compounds.

TSMC also expanded its external R&D partnerships and alliances with world-class research institutions. For example, TSMC is a core partner of IMEC in Belgium, the respected European R&D consortium. TSMC also has strategic agreements with IP providers to enable the development of reusable IPs through the advanced technology nodes. TSMC strengthened its collaborations with key development partners on design-process optimization, and provides funding for nanotechnology researches at leading research universities worldwide to promote innovations and the advancement of technology.

These research efforts enable the Company to continuously offer its customers the foundry-leading, first-to-market technologies and design solutions that contribute to their product success in today’s complex and challenging market environment.

R&D Accomplishments in 2012

R&D Highlights

In 2012, TSMC’s 28nm technology offering added 28nm High Performance Plus (28HPP) and 28nm High Performance Triple-Gate (28HPT). 28HPP and 28HPT achieved 10% faster speed than that in previous 28nm High Performance (28HP) and 28nm High Performance Mobile Computing (28HPM) offered in 2011. 28HPP was qualified and demonstrated first silicon success in early production. 28HPT received first customer tape out in December 2012, and was scheduled to deliver first silicon success by April 2013.

In 2012, TSMC continued to focus on 20nm technology development, including process baseline setup and yield learning, design rule definition and enhancement, SPICE model generation, and reliability evaluation. To offer a leading-edge technology for both digital and analog applications, the Company adopted an advanced lithography process for smaller feature size. With the second generation of high-K metal-gate, more Si strain, and new device structure, the intrinsic transistor performance continues to enhance following Moore's Law. Meanwhile, external resistance can be effectively reduced and controlled by a specially designed process technique. The back-end-of-line (BEOL) interconnect process features extreme low-K inter-metal dielectric materials and copper metallization with the novel low-resistance scheme. The logic transistor and SRAM bit-cell offering, using the 20nm process, can satisfy high performance System-on-Chip (SoC) applications.

Development of 20nm technology will create superior gate density and chip performance. The cost and complexity of advanced technology will continue to escalate for customers. In 2012, TSMC successfully taped out the process development test vehicle, defect reduction vehicle and product-like yield learning vehicle, on which the advanced ARM-core block was included. With the vehicle and process development, TSMC provided V1.0 process flow, design kits (design rules, SPICE models, and PDK files) and intellectual property (IP) to help reduce foundry-access costs in 2012. The Company achieved its outstanding transistor performance target and demonstrated the functional and natural yield of the leading-edge SRAM bit-cells as planned. Besides the internal test vehicles, the Company also launched two public cyber shuttles in April and November 2012. More than 10 customers took the shuttles and verified their IPs. TSMC’s high-performance 20nm process enters risk production in first quarter of 2013.

TSMC completed 16nm technology definition and began 16nm technology development in 2012. In order to further extend Moore's Law, the FinFET transistor, an advanced 3D device structure, was introduced in the 16nm technology in addition to the third generation of high-K metal gate, the fifth generation of strain technology and advanced 193nm lithography. As a result, the 16nm technology offers substantial power reduction for the same chip performance, a must for advanced mobile applications as compared to technologies built with the traditional planar structure.

In 2012, TSMC achieved significant progress on test vehicle generation, process baseline setup, design rule definition, SPICE model generation and reliability evaluation. TSMC successfully taped out a process development test vehicle, provided customers early design kits (design rules and SPICE models) and demonstrated functional yield on the FinFET-based SRAM bit-cells according to plan.

20nm lithography progressed steadily in 2012. There has been continuous learning and improvement in material quality, process recipe robustness, and litho-cell maintenance that resulted in robust patterning solutions. The achieved defect learning and D0 goals enable successful yield learning on SRAM qualification vehicles and several key customer tape-outs.

Lithography for the 16nm node signifies the introduction of novel patterning techniques to achieve 48nm pitch FinFET, especially to ensure sufficient coverage and planarization of high aspect ratio topography with the 3D device structures. In addition, TSMC has also developed the patterning solution to delineate the tightest single patterning pitch of 80nm for the metal layer enabling further increase of pattern density for customers. Building on the learning of the 20nm node, TSMC has automated the in-line pilot run process and its control that enable fast cycle time for SRAM development and yield learning.

The pathfinding for 10nm node has been started on immersion scanners. This technology will become more sophisticated and play a key role as the process baseline, based on considerations of cost and next-generation tool availability. Innovative processes are being developed to deal with the process control challenges brought with this technology node. Optical proximity correction has solved the process problem. Both cost and measurement accuracy were greatly improved with this change.

Development of EUV lithography and multiple e-beam direct write is aimed at the 7nm node because of late availability. Nevertheless, the 10nm node will be used to exercise these technologies.

At the front of specialty technology, R&D lithography has further extended the limitation of scanners in the 8-inch fabs, to shrink the design rules and help customers gain more gross dies per wafer to reduce the die cost. R&D has transferred multiple eFlash technologies for manufacturing and delivered eMRAM and eRRAM lithography technologies. For MEMS, R&D has developed and transferred the manufacturing technology for microphones and accelerometers.

TSMC continues to work with exposure-tool partner ASML in the development of immersion and EUV lithographic technologies. Faced with delays in the EUV source technology, capabilities of 193nm immersion scanners are being extended with more resolution-enhancement features, tighter specifications, and higher throughput to enable multiple patterning. In the meantime, using NXE3100 beta-tool in Fab 12, we have been developing single-patterning EUV processes for 10nm and 7nm applications, with associated mask and resist technologies. However, the application of EUV lithography in high-volume manufacturing of these nodes will depend on the success of the EUV source technology to reach over 100 wafers per hour.

The KLA-Tencor REBL multiple-e-beam direct-write tool is being extensively studied for feasibility, performance, and improvements. A TSMC team from the design, CMOS, MEMS, and packaging areas is jointly developing and fabricating the dynamic pattern generation chip for the REBL system. Two test stands for qualification of dynamic pattern generation and resist testing are being built and will be delivered to the TSMC Fab 12 GIGAFAB™ facility in 2013. Two scanner companies are performing sizing feasibility for multiple e-beam direct-write lithography. Multiple e-beam direct-write lithography not only has the potential for imaging critical layers, it also offers cost reduction potential for non-critical layers and 450mm wafers.

Mask technology is an integral part of advanced lithography technology. In 2012, TSMC completed the development of the mask technology for the 20nm node to enable double patterning. TSMC’s R&D mask facility received more state-of-the-art mask processing tools to enable engineers to complete the development of mask technologies for the 16nm and 10nm nodes in the coming years. Development of mask technology for EUV lithography has been underway with its unique requirements in e-beam writing, etching, inspection, repair, and verification. As a core member of SEMATECH and a joint-development partner of EIDEC, TSMC is an active participant in the development of key infrastructure pieces for EUV masks such as the actinic repair verification tool and the actinic inspection tool of EUV blanks.

Integrated Interconnect and Packaging

In 2012, TSMC became the world’s first foundry to provide full system integration turn-key solutions to customers. The Company developed and delivered backend technologies starting from advanced back-end-of-line (BEOL) interconnect, to the production-ready fine pitch silicon interposer with through silicon via (TSV) & chip stacking, and all the way to the advanced wafer-level-chip scale packaging (WLCSP) including fan-in and fan-out, and ultra fine pitch large die lead-free flip chip packaging. TSMC can offer our customers corresponding design tools, technology and mass production capability. Such options were made available to customers in 2012. Advanced BEOL interconnection is further refined and extended with innovative damascene processes. And the flip chip packaging technology envelope was expanded to larger chip size and finer bump pitches for advanced technology nodes (28nm and 20nm). Efforts are also made to include fan-in and fan-out wafer level packaging technology in our offerings to customers. The solution has been qualified by selective customers.

Advanced interconnects with low resistance/capacitance RC delay continued to be the primary focus of TSMC BEOL technology development in 2012. For 16nm node and beyond, we have developed a new interconnect scheme to achieve minimum pitch and a new metal patterning to minimize resistance/capacitance RC delay.

At the 20nm node, the effective resistivity of our Cu lines is highly competitive and lower than that projected by the International Technology Roadmap for Semiconductors (ITRS).

To provide innovative and cost competitive lead-free bumping and packaging solutions in 2012, TSMC developed and qualified 28nm technology node Bump-on-Trace packaging technology with ultra-fine pitch array (100μm pitch) Cu-bump for mobile devices. The Company expanded the lead-free packaging technology envelope to 20nm node and offered a wide variety of lead-free flip chip packaging technologies for both mobile/handheld and high performance applications to enhance customers’ competitiveness.

In 2012, R&D completed CoWoS™ process and package qualifications and transferred the technology for production. CoWoS™ solution provides a simple integration process for customers to realize their products with the optimized cost and cycle time. We have also developed the 3D IC 28HPM through transistor stacking (TTS) technology, that can enable customers for applications requiring small form factor, high performance and low power dissipation. Realizing the critical nature of 3D IC thermal management, TSMC has also developed thermal solutions associated with the CoWoS™ process and TTS technologies. Overall, TSMC delivers technology solutions to enable SiP design that includes package design, electrical analysis of package extraction, timing, signal integrity, IR drop, and thermal to physical verification of design rule check (DRC) and layout verification of schematic (LVS). Such integrated solution for product realization is available to customers.

Advanced Transistor Research

Continuous quest for high performance and low power drives innovation and research in transistor architecture in advanced logic technologies across all segments. TSMC invested heavily in alternative high speed and low power channel materials other than silicon, such as germanium and III-V compounds. New concepts of transistor structures employing innovative nanotechnology are also under intensive investigation.

Spectrum of Technology

In addition to CMOS logic technology, TSMC continues to conduct research and development on a broad mix of capabilities. The Company enhanced its SoC roadmap, with higher integration and more variants.

TSMC developed full scope 28nm oxi-nitride and poly-Si based RFCMOS technology for next generation RF transceivers (ex. 4G LTE) with the advantages of low power & low cost. Besides standard-Vt and low-Vt devices, extreme-low-Vt devices were also included for larger design margins and smaller active-power consumption. TSMC delivered a CMOS process compatible technology for enabling cellular RF switch applications on Si to compete with traditional compound semiconductor- based process. TSMC enabled production of the IPD (Integrated Passive Device) technology, specifically for rapidly expanding mobile devices.

In 2012, TSMC’s HV/ Power technologies collectively shipped more than 1 million wafers to customers. On top of the production base, R&D team released the second generation of 0.18 BCD technology, and the first product from a partner customer has shipped engineering samples to system customer.

In 2012, 80HV for smartphone display driver chips was released to production. And a customized derivative of the technology has also supported partner customer’s lead product design. Other than small panel for smartphone, we also have been developing a 0.11μm technology specifically for tablet applications.

In 2012, TSMC’s modular MEMS technology for accelerometer was released and supported the partner customer production ramping. A microphone project for high-resolution noise cancellation applications was executed.

In 2012, TSMC achieved several milestones in embedded flash technologies at 65/55nm node. The split-gate cell at the 65nm node was qualified for automotive process and is currently in production. For other NOR-type cells, a customer is shipping several prototypes for sampling. For hybrid cells, products for 100k chip card application are in sampling.

At the 40nm node, TSMC has engaged with leading IDMs to develop nitride film storage flash cell and NOR type cell for both automotive and consumer applications.

Technology Platform

TSMC equips modern IC designers with a comprehensive design infrastructure required to optimize productivity and cycle time. This includes design flow for electronic design automation (EDA), silicon-proven building blocks such as libraries and IPs, simulation and verification design kits such as process design kit (PDK) and tech-files. All these are built on top of the technology foundation, and each technology needs its own design infrastructure to be usable for designers. This is the concept of a technology platform.

TSMC’s technology platforms reflect the culmination of years of work by TSMC and its alliance partners. The Company has added additional deliverables to its Open Innovation Platform® initiative to further enhance its technology platforms every year since OIP was launched in 2008.

In October 2012, TSMC announced full delivery of 20nm design ecosystem through OIP collaboration. TSMC’s 20nm design ecosystem is ready with foundation design collaterals such as DRC, LVS, and PDKs; foundation IPs, including standard-cell libraries, standard I/O, e-Fuse and memory compilers; and standard interface IPs such as USB, PCI, and DDR/LPDDR. Customers can conveniently download these materials at TSMC Online. In addition, new design enablement of EDA tools is updated regularly to satisfy 20nm technology requirements.

TSMC addressed the most critical design challenges through two technology- specific Reference Flows in 2012: 20nm Reference Flow and CoWoS™ Reference Flow. Through these two new reference flows, customers gain access to needed solutions in order to design in TSMC 20nm technology and CoWoS™ technology.

In October 2012, TSMC also announced the foundry segment’s 20nm Custom Design Reference Flow, and the fourth revision of the Radio Frequency Reference Design Kit (RF RDK), providing needed design enablement for custom design and RF design.

To ensure timely enhancement of OIP Ecosystem partners’ tool compliance with new process requirements, TSMC works with EDA partners to proactively certify EDA tool readiness and publish a report on TSMC online.

Starting from 20nm, the coverage of EDA certification further expanded from DRC, LVS, RC extraction, placement and routing, to static timing analysis, electro-migration, IR drop and custom design.

In order to lower the barrier of technology adoption for customers, TSMC introduced the Integrated Sign-Off Flow (ISF) in 65nm/55nm in 2009, announced 40nm ISF in 2011 and 28nm in 2012. ISF is a production-proven design flow based on TSMC’s expertise accumulated over the years. ISF started to bear fruit in 2010, and enabled a large number of first-time customers to leapfrog from 0.13μm node to 65nm/55nm node. The introduction of 40nm ISF has further helped customers seize more business opportunities to jumpstart their product solutions, with examples of successful tape-outs for mobile processor application and 3G/4G communication from China in 2011. The newly revealed 28nm ISF in 2012 helped customers seize opportunities in mobile communication with designs in 28nm node.

The Soft-IP Alliance Program aims to improve soft-IP readiness for advanced technology nodes and to drive earlier time-to-market. Soft-IP has historically been process technology independent and therefore not optimized for power, performance, and area considerations. Given the ever-increasing need of first-time silicon success and early time-to-market for highly integrated circuits, such as System-on-Chip (SoC), close technical collaboration between the foundry and the IP provider is imperative to emphasize this critical trade-off.

In 2011, TSMC set up a dedicated quality management system to drive for highest quality assurance for soft-IP continuing the successful story of excellent quality records as seen in hard-IP. Customers can access soft-IP9000 assessment status reports of soft-IPs through TSMC Online. In 2012, the new soft-IP Handoff Package (the soft-IP Kit 2.0) is ready for soft-IP Partners. Soft-IP Kit 2.0 provides an enhanced set of checks that covers such additional design checks as early physical implementation aspects (e.g., area, timing, and congestion) and advanced formal lint checks.

Design Enablement

Customers can design directly using TSMC technologies through the Company’s internal design team as well as via alliance partners. TSMC’s technology platform provides a solid foundation for design enablement.

Tech File and PDK

Because of TSMC’s broader, earlier, and deeper collaboration with customers through the OIP initiative, customers gain greater benefit from TSMC tech-files and process design kit (PDK). The benefits are evidenced by a significant increase to more than 100,000 downloads in 2012, from 50,000 downloads in 2011. TSMC also increased resources to meet the high demand on PDK for specialty technologies.

Library and IP

TSMC and its alliance partners offer TSMC’s customers a rich portfolio of libraries and IPs. These reusable building blocks are essential for many design projects. In 2012, over 60% of new tape-outs at TSMC adopted one or more libraries or IPs from TSMC and/or its IP partners. To support the high demand, TSMC also invested resources to expand its library and silicon IP portfolio. The total number of library or IP content in the portfolio, including soft IPs, increased to 5,400 in 2012, compared with 3,740 in 2011.

Design Methodology and Flow

TSMC announced in October 2012 the full delivery of 20nm support within Open Innovation Platform® (OIP) design infrastructure.

TSMC’s 20nm deign ecosystem is ready with foundation design collaterals such as DRC, LVS, and PDKs; foundation IPs, including standard-cell libraries, standard I/O, e-Fuse & memory compilers; and standard interface IPs such as USB, PCI, and DDR/LPDDR. Customers can download these files at TSMC Online. Collaboration with the EDA community for 20nm has been very thorough in order to achieve tool consistency for improved design results.

20nm Reference Flow features new design solutions/capabilities in place-and-route, RC extraction, DRC, timing analysis, electro migration and IR-drop to enable 20nm designs in double patterning and with characteristics that closely match silicon behavior. CoWoS™ Reference Flow was announced in October 2012. The emerging 3D integration and process technologies allow the designs with multi-technology support. CoWoS™ Reference Flow enables heterogeneous integration across multiple technologies and memory integration through Wide-IO. In order to satisfy the demands of emerging systems for scaling, performance and functionality, the CoWoS™ Reference Flow provides a complete analysis suite for power integrity, thermal analysis, simultaneously switching noise and innovative DFT and place-and-route solution. With cooperating TSMC ecosystem partners, CoWoS™ design methodology provides the most cost-effective solution for the TSMC recommended design environment. The CoWoS™ design platform can take all benefits of advanced nodes and mature technologies in a very flexible way to achieve target design requirements.

20nm Custom Design Reference Flow enables double patterning capability. It provides solutions to process requirements that are significant in 20nm, including a direct link with simulators for the verification of voltage-dependent DRC rules, an integrated layout-dependent-effect solutions and handling of high-K metal-gate edge effect.

The updated RF RDK provides a solution to address common challenges that RF designers encounter. RF RDK 4.0 offers flexible five-terminal MOS device and accurate noise model for slow wave transmission line. RDK 4.0 also offers comprehensive electro-magnetic work flow for radio-frequency passive device synthesis through integrated-passive-device, 60GHz and scalable VCO reference example to assist customers in inductor design.

Intellectual Property

A strong portfolio of intellectual property rights strengthens TSMC’s technology leadership and protects our advanced and leading edge technologies. In 2012, TSMC received a record breaking 647 U.S. patents, as well as 300+ issued patents in Taiwan and the PRC, and other patents issued in various other countries. In 2012, TSMC achieved a patent milestone: breaking into the “Top 50” U.S. patent grants in 2012. TSMC’s patent portfolio is now approximately 20,000 patents worldwide (includes patent applications in queue). We continue to implement a unified strategic plan for TSMC’s intellectual capital management. Strategic considerations and close alignment with the business objectives drive the timely creation, management and use of our intellectual property.

At TSMC, we have built a process to extract value from our intellectual property by aligning our intellectual property strategy with our R&D, business objectives, marketing, and corporate development strategies. Intellectual property rights protect our freedom to operate, enhance our competitive position, and give us leverage to participate in many profit-generating activities.

We have worked continuously to improve the quality of our intellectual property portfolio and to reduce the costs of maintaining it. We plan to continue investing in our intellectual property portfolio and intellectual property management system to ensure that we protect our technology leadership and receive maximum business value from our intellectual property rights.

TSMC University Shuttle Program

The TSMC University Shuttle Program was established to handle MPW (Multi-Project Wafer) access requests by qualified professors at leading research universities worldwide. To participating professors, TSMC University Shuttle Program provides annual pre-approved access to quality technologies, including 65nm, 40nm process nodes for analog/mixed-signal circuits and RF design, and 0.11μm/0.18μm process nodes for micro-electromechanical system designs. For very advanced logic design and SRAM researches, the 28nm process node is provided to special university projects. To TSMC, the key performance indices are the 3Rs: Recruiting, Research results transfer from universities to TSMC, and Recognition.

Participations in the TSMC University Shuttle Program include the active participation of major university research groups: in the U.S., M.I.T., Stanford University, UC Berkeley, Harvard University, and UCLA; in Taiwan, National Taiwan University, National Chiao-Tung University, and National Tsing-Hua University; in China, Tsing Hua University in Beijing, and Hong Kong University of Science and Technology, and in Singapore, Nanyang Technological University.

  

The TSMC University Shuttle Program serves as an effective bridge to link motivated professors and graduate students in leading research universities worldwide with enthusiastic directors and managers at TSMC to contribute to newer level of excellence in advancing technologies and in nurturing new generations of talent in the semiconductor field.

TSMC’s University Shuttle Program has been very effective and is praised by professors around the world. They have recognized that this Program allows their graduate students to implement exciting designs ranging from low-power memories, analog-to-digital converters and digital designs to advanced radio-frequency and mixed-signal bio-medical systems. This is a truly “win-win” collaboration. In 2012, TSMC received specific letters of appreciation from professors at M.I.T., Stanford University, UC Berkeley, Harvard University, UCLA, National Taiwan University and National Chiao-Tung University.

Future R&D Plans

In light of the significant accomplishments of TSMC’s advanced technologies in 2012, the Company plans to continue to grow its R&D investments. The Company plans to reinforce its exploratory development work on new transistors and technologies, such as 3D structures, strained-layer CMOS, high mobility materials and novel 3D IC devices. These studies of the fundamental physics of nanometer CMOS transistors are core aspects of our efforts to improve the understanding and guide the design of transistors at advanced nodes. The findings of these studies are being applied to ensure our continued industry leadership at the 28nm and 20nm nodes and to extend our leadership to the 10nm and 7nm nodes. One of TSMC’s goals is to extend Moore's Law through both innovative in-house work and by collaborating with industry leaders and academia. We seek to push the envelope in finding cost-effective technologies and manufacturing solutions.

TSMC intends to continue working closely with international consortia and lithography equipment suppliers to ensure the timely development of 193nm high-NA scanner technology, EUV lithography, and massively parallel e-beam direct-write technologies. These technologies are increasingly important to TSMC’s process development efforts at the 10nm, 7nm, and smaller nodes.

TSMC continues to work with mask writing and inspection equipment suppliers to develop viable mask making technology to help ensure that the Company maintains its leadership position in mask quality & cycle time and continues to meet aggressive R&D, prototyping and production requirements.

With a highly competent and dedicated R&D team and its unwavering commitment to innovation, TSMC is confident of its ability to deliver the best and most cost-effective SoC technologies for its customers, thereby supporting the Company’s business growth and profitability.

TSMC R&D Future Major Project Summary

Project Name Description Risk Production (Estimated Target Schedule)
16nm logic platform technology and applications Next-generation technology for both digital and analog products 2013
10nm logic platform technology and applications Exploratory technology for both digital and analog products 2015
3D IC Cost-effective solution with better form factor and performance for SIP 2013 - 2014
Next-generation lithography EUV and multiple e-beam to extend Moore's Law 2014 – 2016
Long-term research Special SoC technology (including new NVM, MEMS, RF, analog) and 10nm transistors 2013 – 2015
The above plans account for roughly 70% of the total R&D budget in 2013, while total R&D budget is currently estimated to be around 8% of 2013 revenue.