Manufacturing Excellence
GIGAFAB Facilities
TSMC’s 12-inch fabs are a key part of its manufacturing strategy.
TSMC currently operates three 12-inch GIGAFAB fabrication facilities – Fab 12, Fab 14, and Fab 15 – whose combined capacity reached 3,936,000 12-inch wafers in 2012. Production within these three facilities supports 0.13μm, 90nm, 65nm, 40nm, 28nm, and 20nm process technologies, and their sub-nodes. Part of the capacity is reserved for research and development work and currently supports 16nm, 10nm and beyond technology development. TSMC has developed a centralized fab manufacturing management for the customers’ benefit of consistent quality and reliability performance, greater flexibility of demand fluctuations, faster yield learning and time-to-volume, and minimized costly product re-qualification. It enables Fab 15 to fast ramp 28nm capacity from zero to 50,000 wafers output per month in eight months to satisfy customers’ demand.
Engineering Performance Optimization
Highly sophisticated information technology (IT) solutions, such as advanced equipment control, fault detection and diagnosis, engineering big data mining, and centralized operation platforms, are implemented to optimize TSMC equipment, process and yield performance. They also improve production efficiency, effectiveness, and engineering capability via information integration, workflow optimization and automation.
Advanced analytical methods identify critical equipment and process parameters that are linked to device performance. Methodologies such as virtual metrology, yield dissection and management integrate Advanced Process Control (APC), Fault Detection Classification (FDC), Statistical Process Control (SPC), and Circuit Probe data in order to optimize equipment performance to match device performance.
Accurate modeling and control at each process stage drives intelligent module loop control. The process control hierarchy dispatched via sophisticated computer-integrated manufacturing systems enables optimization from equipment to end product, which achieves precision and lean operation in a high product mix semiconductor manufacturing environment.
Precision and Lean Operations
TSMC’s unique manufacturing infrastructure is tailored for a high product mix foundry environment. Following its commitment to manufacturing excellence, TSMC has equipped a sophisticated scheduling and dispatching system, implemented industry-leading automated materials handling systems, and employed Lean Manufacturing approaches to provide customers with on-time-delivery and best-in-class cycle time. Real-time equipment performance and productivity monitoring, analysis, diagnosis and control minimize production interruption and maximize cost effectiveness.
450mm Wafer Manufacturing Transition
TSMC joined the Global 450mm Consortium (G450C) located in the College of Nanoscale Science and Engineering (CNSE) of New York University at Albany, New York. The consortium includes five IC makers and CNSE (which represents New York State and provides the clean room facility), as well as key 450mm tool suppliers as associate members.
Currently, TSMC has 16 experienced employees working in the consortium. TSMC has assumed the Operation GM position in the consortium and commits to lead the industry for a cost-effective 450mm transition. The clean room of G450C in Albany has been ready for tool installation since Q1 2013. The majority of the tools will be installed in 2013.
Besides 450mm tool readiness, TSMC is also developing novel 450mm operation to bring the maximum value of semiconductor wafer fabrication to customers, including advanced quality and the most competitive cycle time in advanced technology. 450mm will be a new era of semiconductor manufacturing with new manufacturing capability advanced from today’s leading edge technology.
Raw Materials and Supply Chain Risk Management
In 2012, TSMC continued Supply Chain Risk Management meetings periodically to integrate Company resources from materials management, fab operations, risk management and quality management. TSMC worked with its suppliers to enhance the performance of quality, delivery, risk management, and to support green procurement, environmental protection and safety.
Raw Materials Supply
| Major Materials | Major Suppliers | Market Status | Procurement Strategy |
|---|---|---|---|
| Raw Wafers | F.S.T. MEMC S.E.H. Siltronic SUMCO |
These five suppliers together
provide over
90% of the world's wafer supply. Each supplier has multiple manufacturing sites in order to meet customer demand, including plants in North America, Asia, and Europe. |
|
| Chemicals | Air Products ATMI BASF Dow KANTO-PPC MGC |
These six companies are the major suppliers for bulk and specialty chemicals. |
|
| Litho Materials | AZ Dow JSR Nissan Shin-Etsu Chemical Sumitomo T.O.K. |
These seven companies are the major suppliers for worldwide litho materials |
|
| Gases | Air Liquide Air Products Linde Taiyo Nippon Sanso |
These four companies are the major suppliers of specialty gases. |
|
| Slurry, Pad, Disk |
Asahi Glass Cabot Microelectronics DA Nano Dow Chemical Fujifilm Plannar Solutions Fujimi Hitachi Chemical Kinik 3M |
These nine companies are the major suppliers for CMP materials. |
|
Suppliers Accounted for at Least 10% of Annual Consolidated Net Procurement
Quality and Reliability
A characteristic of TSMC’s industry reputation is its commitment to providing customers with the best quality wafers and service for their products. Quality and Reliability (Q&R) services aim to achieve “quality on demand” to fulfill customers’ needs regarding time-to-market, reliable quality, and market competition over a broad range of products.
Q&R technical services assist customers in the technology development and product design stage to design-in their product reliability requirements. Since 2008, Q&R has worked with R&D to successfully establish and implement new qualification methodology for High-k/Metal Gate (HKMG). Q&R also works with design services on embedded memory, high voltage, e-Fuse and MEMS IP developments to expand TSMC’s design portfolio. Since 2009, Q&R has worked with R&D and the design service team to improve the quality of design kits through integrated R&D and design quality platform. In 2012, Q&R continued to work with R&D and the design team to develop DRM infrastructure with iEDA layout platform. Q&R also deployed an SRAM cell review system to improve bit cell change quality of third parties and customers. Q&R has been collaborating with SEMI to establish an IC Quality Committee since May in order to enhance product quality of the semiconductor supply chain. For backend technology development, Q&R worked with R&D, BTSD (Backend Technology and Service Division) and Product Engineering to complete the CoWoS technology development and production transfer. After establishing Power Cycling capability and methodology in 2011, Q&R will further extend backend characterization by adding system-level temperature cycling, bending, drop and vibration tests in 2013.
Q&R has deployed systems to ensure robust quality in managing production and in design services, including third-party IP management, to meet the business requirements of customers. Q&R also implemented innovative statistical matching methodologies to enhance manufacturing quality, including matching of facility, metrology and process tools, wafer acceptance test (WAT) data and reliability performance. In 2011, Q&R tightened the post-fab outgoing visual inspection criteria for wafer quality improvement to AQL 0.4% from AQL 0.65%.
To sustain production quality and to minimize risk to customers when deviations occur, manufacturing quality monitoring and event management span all critical stages – from raw material supply, mask making, and real-time in-process monitoring, to bumping, wafer sort and reliability performance. Advanced failure and materials analysis techniques are also developed and effectively deployed in process development, customer new product development and product manufacturing. In addition to adapting analytical techniques to aid in the release and monitoring of advanced Fab tools and processes for advanced technology nodes, state-of-the-art electron microscopy, chemical analysis and fault isolation equipment were added at a record pace in 2012 to support development activities of the 20nm and 16nm technology nodes.
In compliance with the electronic industry’s lead-free and green IC package policy, Q&R qualified and released lead-free bumping to satisfy customer demands, and made lead-free bump package possible for 0.13μm, 45nm, 40nm and 28nm technology products by collaborating with the major outsource assembly & testing subcontractors (OSAT). This enabled TSMC customers to introduce and ramp lead-free products with excellent assembly quality. In 2012, TSMC Q&R ramped wafer-level Chip Scale Package (CSP) to 20K per month and lead-free to 40K per month without major quality issues. For mainstream technologies, Q&R qualified ultra, extreme low leakage and high endurance embedded Flash IP, IPD (Integrated Passive Device), hybrid of Copper, Copper-Aluminum technology with customers. Q&R continues to build reliability testing and monitoring to ensure excellent manufacturing quality of automotive, high-voltage products, CMOS image sensors and embedded-Flash memory products.
TSMC Q&R is also responsible for leading the Company towards the ultimate goal of zero-defect production through the use of continuous improvement programs. Periodic customer feedback indicates that products shipped from TSMC have consistently met or exceeded their field quality and reliability requirements. In 2012, a third-party audit verified the effectiveness of the TSMC quality management system (including R&D labs) in compliance with ISO/TS 16949:2009 and IECQ QC 080000 certificates requirements.


