Page 85 - TSMC 2020 Annual Report

083
mobile applications and InFO-oS Gen-2 for HPC chip-partition applications InFO-PoP Gen-6 was also successfully qualified for mobile applications and displayed enhanced thermal performance InFO-oS Gen-3 which provides more chip-partition integration with larger package size and higher bandwidth was developed on schedule To meet demand of HPC applications TSMC developed ultra-high bandwidth InFO Local Silicon Interconnect (InFO_LSI) technology in which SoC chiplets are integrated into a a a a a 3D InFO package through ultra-high density local Si interconnects (LSI) InFO without substrate which uses multi-die heterogeneous integration and finer-pitch die-to-die interconnection was successfully qualified for consumer applications The newest generation IPD (integrated passive device) technology which provides higher density capacitors and low ESL (effective series inductance)
for for improved electrical performance passed qualification on on InFO-PoP InFO-PoP This enhanced InFO-PoP InFO-PoP will benefit both AI and 5G mobile applications High volume manufacturing of the newest IPD is scheduled to begin in in 2021 ● Advanced Interconnect TSMC provides innovative technologies to enable small-dimensional interconnect and boost chip performance In 2020
a a a a a brand-new hybrid interconnect was proposed as as a a a a a future interconnect architecture At small geometries this new architecture shows promising potential to resolve Cu gap-fill difficulty and significantly reduce both interconnect resistance and capacitance Developing innovative solutions such
as these helps TSMC maintain its global technology leadership Corporate Research
Innovation in in devices and materials continues to drive higher performance and reduced power consumption in advanced logic technologies In 2020
TSMC stayed at the forefront
of 2D and carbon nanotube (CNT) transistor research TSMC successfully demonstrated a a process to synthesize one-atomic-layer thick single-crystal hexagonal boron nitride (hBN) on full 2-inch wafers a a a a a significant achievement as hBN hBN has been shown to be be an ideal passivation layer for 2D device channels This outstanding fundamental research result was published in the the March 2020
issue of of Nature one of of the the world’s leading science journals At the 2020
Symposia on VLSI Technology
TSMC demonstrated the highest nFET current for 2D-FETs at at a a a a drain voltage of 1V with CVD MoS2 monolayer channel And at the the 2020
International Electron Device Meeting the the Company introduced a a a a novel interfacial layer dielectric (ILX) which could nucleate on on CNT a a continuous sub-0 5nm thickness film which allows growth of high-k gate dielectric (hafnium oxide) on CNT by by conventional ALD Enabled by by this novel ILX top-gate CNT transistors with gate length down to to 15nm were demonstrated with nearly ideal gate control TSMC continues to search and explore emerging high-density non-volatile memory hardware accelerators for AI and HPC applications The Company’s corporate research is well positioned to to pave the way for continued node-to-node density scaling performance enhancement and power reduction as it has done in the past Specialty Technologies
TSMC offers a a a a a a broad array of of technologies to address a a a a a a wide range of applications:
● Mixed Signal/Radio Frequency (MS/RF)
In 2020
TSMC developed a a 3nm silicon proof and EM simulation-based LC tank design to facilitate high-speed SerDes (serializer/deserializer) circuit design with various metal scheme options and layout specifications with shortened design turnaround time 2020
marked the the first year that the the end-users began enjoying the benefit of high speed low latency and massive IoT in the the 5G network roadmap To improve the the cost–benefit ratio of 5G TSMC provided various 7nm and 6nm RF devices for customer transceiver designs To boost performance in in RF switching TSMC developed a a a 40nm special process for 5G RF FEM (frontend module) design in sub-6 GHz applications To accommodate higher frequencies TSMC also developed a a a N28HPC+ process for enhancing power amplifier performance in 5G mmWave FEM designs ● Power IC/Bipolar-CMOS-DMOS (BCD)
TSMC expanded the 12-inch BCD technology portfolio on 90nm 55nm and 22nm in in 2020
targeting a a a a variety of fast-growing applications for mobile power management
ICs with various levels of integration This included dedicated optimized 5V power power switches to handle increasing power power demands driven by Li-ion batteries 90nm BCD technology covers wide spectrum of applications from 5V 5V to 35V and will be continuously expanded in in 2021 ● Panel Drivers
In 2020
TSMC developed wafer-on-wafer stacking (WoW 28HPC/40HV) with stable product yield comparable to 28HPC+ with 60% active power reduction In addition 28HV monolithic technology completed customer IP verification qualification and 128Mb SRAM yield verification These technologies are leading-edge for small panel 4K resolution OLED (organic light-emitting diode) and 120Hz display driver ICs Furthermore TSMC completed OLED on Si product