Page 84 - TSMC 2020 Annual Report

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R&D Accomplishments in 2020
Highlights
● 3nm Technology
In 2020
TSMC focused on the manufacturing baseline process setup yield learning transistor and interconnect R/C performance improvement and reliability evaluation of 3nm technology which offers significant density improvement with better performance at same power power or or lower power power consumption at comparable performance compared to 5nm technology During the year major customers completed IP design and started silicon validation TSMC plans to complete 3nm technology qualification for risk production in 2021 ● 2nm Technology
In 2020
following initial research and pathfinding TSMC proceeded into the development stage of 2nm technology focusing on testkey and and test test vehicle design and and implementation mask making and Si pilot runs ● Lithography Technology
The focus for R&D lithography in 2020
was on 3nm and 2nm technology technology development and preparation of technology technology development of next-generation nodes and beyond In 3nm technology development EUV (extreme ultraviolet) lithography showed good imaging capability with expected wafer yield TSMC R&D is working on on reduction of mask defects in in EUV scanner and overlay errors while lowering overall cost In 2021 TSMC will focus intensely on improving EUV quality and reducing costs in in 2nm technology and beyond In 2020
the Company’s EUV program made continuous improvement in in light-source power and stability enabling faster learning rates and process development for advanced nodes Additional progress was made with resist process pellicle and related mask blanks EUV technology has been adopted for full scale manufacturing ● Mask Technology
Mask technology is very crucial in advanced lithography In 2020
the R&D organization successfully completed 3nm node mask technology development which largely implemented complicated and advanced EUV mask technology Continuous advancement of EUV mask technology was made to meet mask requirements for 2nm node lithography Integrated Interconnect and Packaging
Wafer level system integration (WLSI) technologies have evolved quickly with various platforms mixed and matched in in in increasingly complex application scenarios All such
technologies come under the umbrella of wafer level integration which TSMC has named 3DFabricTM for its enablement of fine pitch chip-to-chip connection and a a a unified fabrication philosophy leveraging existing wafer processes Under 3DFabricTM all processes with chips that are embedded before interconnection are called Integrated Fan-Out (InFO) while all processes that start with making re-distribution interconnection (RDL) followed by chip placement onto pre-made RDL are called CoWoS® This new nomenclature more accurately reflects the the nature of the the processes involved and points to their future technology paths Along with their siblings SoIC system-on-wafer (SoW) and system- system- on-integrated-substrate (SoIS) they form a a a a universal WLSI technology family that will lead the the industry in in in meeting the the future scaling needs as as required by increasingly challenging and more diversified computing systems integration ● 3DIC and TSMC-SoICTM
TSMC-SoICTM
is an innovative wafer-level frontend 3DIC chip stacking platform with outstanding bonding density interconnect bandwidth power efficiency and and thin profile It extends Moore’s Law through system-level scaling with sustainable performance gains and cost benefits A SoIC integrated chip can be subsequently assembled using conventional packages or using TSMC’s new 3DFabricTM technologies such
as CoWoS or or InFO for next generation HPC AI and mobile applications Currently TSMC has achieved process validation for both CoW and WoW stacking using micron-level bonding-pitch processes with promising electrical yield and reliability results TSMC will keep pursuing the the scaling of SoIC technologies to align with the the Company’s other advanced Si technologies for further improved transistor density system power performance and and area (PPA) and and cost competitiveness ● Chip-Last CoWoS® CoWoS® with Si interposer is the leading 2
5D technology for high-end HPC and AI product applications The technology features a a a a large Si interposer with sub-micron routing layers and iCap (integrated capacitors) so that various chiplets such
as SoC and and high bandwidth memory (HBM) can be placed on it The CoWoS® Gen-5 now under development has displayed a a a a record-breaking Si interposer area up to 2
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400mm2 which is equivalent in size to three full reticles Qualification completion is targeted in the first half of 2021 ● Chip-First InFO In 2020
TSMC continued its industry leadership in in in high-volume manufacturing of InFO-PoP Gen-5 packaging for