Page 15 - TSMC 2020 Annual Report
P. 15

● 40ULP analog technology platform was established in 2020 This platform is is fully logic compatible and offers analog-friendly low low flicker noise and low low mismatch transistors In addition to to further enhance TSMC’s analog offerings a low TCR silicon chromium (SiCr) thin film
resistor and and a a a a RTS noise guideline are being developed and and expected to complete in 2021 For analog and mixed-signal applications 40ULP analog platform supports customers’ needs for for optimal logic performance and density low power consumption and superior analog device enhancements with a a a a cost-effective advantage 12-inch 40nm Bipolar-CMOS-DMOS (BCD) Plus technology passed qualification in 2020 The Company has helped customers complete new tape-outs and this technology is is expected to start volume production in 2021 As resistive random access memory (RRAM) can be integrated this technology can support customers’ designs for special applications requiring heavy firmware such as wireless charger chips to enhance product performance and offer better cost advantages 0 0 13μm Silicon on on on Isolator (0 13SOI) technology on on on 8-inch wafers successfully entered volume production in 2020 for customer products of sub-6GHz RF RF front-end module (RF FEM) including smartphones and wireless local area networks (WLANs) following the the delivery of the the first RF process design kit in 2019 TSMC’s 0 0 13SOI technology provides high cutoff frequency (fT) and low on on resistance-off capacitance (Ron-Coff) to support low noise amplifier (LNA) and RF switch product designs 12-inch 0 13μm Bipolar-CMOS-DMOS (BCD) plus technology completed phase-1 continual improvement process (CIP) in in 2020 and significantly improved the specific on resistance (Rsp) of some power devices by more than 20% The corresponding process design kit was available and phase-2 CIP is expected to to be completed in 2021 Compared to to the previous 0 13μm BCD technology technology this technology technology provides continuous performance improvement and features enhancement for power management applications in high-end smartphones 0 0 0 18μm BCD third generation technology passed AEC-Q100 qualification in 2020 Compared to the second generation BCD technology technology this technology technology provides better cost competitiveness Gallium nitride (GaN) on on silicon technology was further enhanced to integrate GaN power switches with drivers in in both 650V and 100V platforms as as well as as improve reliability to to support customer deigns for higher power density and efficiency solutions for various market applications Both 650V and 100V GaN IC technology platforms are expected to be ready in 2021 ● CMOS Image Sensor (CIS) technology was further refined
to support the strong demand in advanced smartphone cameras In early 2020 TSMC helped customers lead the market in in rolling out 0 8μm pixel products Pixel size was further reduced to 0 7μm within nine months with with timely volume production The smaller pixel size enables 30% higher resolution for CIS with the same chip size ● TSMC successfully manufactured single photon avalanche diode (SPAD) 3D sensing products for customers with 0 13μm Bipolar-CMOS-DMOS technology and 45nm stacked CIS technology in 2020 to capture the growth opportunity of 3D sensing market In addition for stacked CIS technology TSMC further launched 22ULL technology and speeds up 12FFC technology development to support the requirement for higher performance and lower power consumption for for image signal processors (ISP) In the meantime TSMC established an an R&D pilot line of 28nm CIS technology to to support customers in in in developing more advanced CIS devices in in in the future ● TSMC successfully used CMOS MEMS (micro electro- mechanical systems) technology in 2020 to support customers in in delivering monolithic ultrasonic scanners This single-chip device helps customers realize portable ultrasonic scanners at affordable low prices Thus many more people can can have an an an easier access to to ultrasonic scanners to to improve health and living 3DFabricTM - TSMC 3D 3D Silicon Stacking and Advanced Packaging Technologies
● ● ● ● ● ● ● ● In 2020 TSMC introduced 3DFabricTM a a comprehensive family of 3D silicon stacking and advanced packaging technologies which are comprised of frontend TSMC-SoICTM 3D 3D silicon stacking and backend 3D 3D interconnect technologies which include CoWoS® (chip on on wafer on on substrate) and InFO (integrated fan-out) providing customers flexible solutions for integration of chiplets TSMC-SoICTM (System on Integrated Chip) technology features both wafer-on-wafer (WoW) and chip-on-wafer (CoW) processes This allows the stacking of both similar and dissimilar dies greatly improving system performance while reducing a a product’s form factor Continuing to to develop CoW process technology in 2020 TSMC successfully demonstrated WoW technology with good electrical results on on on heterogeneous integration of memory on on on logic and deep trench capacitor (DTC) on on logic applications Successfully developed InFO-PoP (Integrated Fan-Out Package-on-Package) technology which integrates 5nm SoC (System-on-Chip) and and DRAM (dynamic random access memory) for advanced mobile device applications This technology helped deliver customer products to to market in high volume in 2020 

   13   14   15   16   17