Page 75 - TSMC 2018 Annual Report

remaining patterning issues As for 5nm development EUV (extreme ultraviolet) lithography showed promising imaging capability with expected good wafer yield R&D is working on EUV cost reduction reduction mask defect reduction reduction in scanner and mask-making capability improvement In 2019 TSMC will focus intently on improving EUV EUV quality and adopting more EUV EUV layers in 3nm technology and beyond In 2018 the EUV program made continuous improvement in light-source power and stability which has enabled faster learning rates and process development for advanced nodes Additional progress was made with resist process pellicle and related mask blanks as as EUV technology moves closer to full scale R&D and manufacturing readiness • M M a a a s s s k k T e e c c h h n n n o o o o l l o o o o g g y y Mask technology is an an integral part of advanced lithography In 2018 R&D successfully implemented EUV mask technology into 7nm+ and 5nm nodes Solid progress was made on the production yield and the reduction of blank native defects to meet high-volume manufacturing requirements Integrated Interconnect and Packaging
Wafer level system integration (WLSI) is built upon TSMC’s wafer processes and capacity core competency to to meet customer system-level and packaging needs in in performance power profile cycle time and cost WLSI encompasses several complementary platforms including TSMC-SoICTM CoWoS® InFO and Under- Bump-Metallurgy Free Integration (UFI) Customers can leverage TSMC’s unique wafer-to-package turnkey services for optimal time-to-market of highly competitive products • 3D IC IC IC and TSMC-SoICTM TSMC-SoICTM (System-on-Integrated Chips) TSMC-SoICTM is an innovative frontend wafer-process-based platform that integrates multi-chip multi-tier multi-function
and and mix-and-match technologies to enable high high speed high high bandwidth low power high pitch density and and minimal
footprint and stack-height heterogeneous 3D IC integration This technology not only helps to sustain Moore’s Law regarding chip chip chip partition and on-chip integration but also enables off-chip heterogeneous system-level scaling TSMC has worked with customers to to develop TSMC-SoICTM designs for for high-performance computing system applications • Si Interposer and CoWoS® (Chip on on Wafer on on Substrate)
TSMC continues to see good growth momentum in in CoWoS® demand in in HPC and and AI applications CoWoS® is the main platform for for heterogeneous integration of advanced node SoC chip and and high bandwidth memory (HBM) TSMC’s leadership in this technology is is further strengthened by robust manufacturing yield growing capabilities on larger interposer and package sizes as as as well as as as feature-rich interposers such as as as embedded capacitors in in the Si interposer • Advanced Fan-Out Fan-Out and InFO (Integrated Fan-Out)
In 2018 TSMC continued to lead in in in high-volume manufacturing of InFO-PoP Gen-3 packaging for mobile applications processors and Integrated Fan-Out on on Substrate (InFO-oS) applications InFO-PoP Gen-4 was also successfully qualified for mobile applications and started developing multi-die integration with fine-pitch die-to-die interconnection and InFO-UHD (ultra-high density) for both mobile and HPC applications Based on on InFO- PoP Gen-4 qualification it could have smaller package size with finer RDL (redistribution layer) line BGA (ball grid array) pitch Gen-4 also enhances thermal performance The newly developed InFO-PoP could be stacked with various commercial DRAM devices with with competitive performance This InFO-PoP with with backside RDL will boost penetration into mobile applications and processor applications with wide
coverage from premium
to mid-end market and was High-Volume Manufacturing
(HVM) ready in in 2019 New generation IPD (integrated passive device) technology which provides high density capacitors and low ESL (effective series inductance) for for electrical performance boost passed qualification on on InFO-PoP InFO-PoP Enhanced InFO-PoP InFO-PoP will benefit AI and 5G mobile applications New IPD HVM is scheduled to begin in in 2019 To meet the demands of 5G mobile communications TSMC has developed an an advanced InFO InFO antenna in in package (InFO-AIP) technology in in which the RF chip and millimeter wave antenna are integrated into an an an InFO package InFO-AIP technology provides high performance low- power small-size low-cost solutions for millimeter wave system applications such as 5G mobile video streaming and virtual reality (VR) wireless communications This technology can also support the fast-evolving automotive applications in in car radar auto-driving and driving driving safety • Advanced Interconnect TSMC has made significant progress in chip performance by interconnect time delay reduction The novel Via processes have demonstrated a a a a a a 30% reduction in Via resistance with comparable chip reliability and performance In addition the novel materials and optimized integration approach have been verified with lower capacitance loading and enhanced device reliability TSMC customers could enhance their competitiveness by using these prominent advances in in in interconnect RC (resistance-capacitance) delay 73