Page 102 - TSMC 2024 Annual Report

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in in product design with integrated frontend and backend technologies to meet future computing systems integration scaling needs ● 3DIC and TSMC-SoIC®
TSMC-SoIC®
wafer wafer product is an innovative wafer-level frontend 3DIC chip stacking platform with outstanding bonding density interconnect bandwidth power efficiency and thin profile It extends Moore’s Law through system-level scaling with sustainable performance gains and corresponding cost benefits SoIC integrated chips can be be subsequently assembled by using conventional packages or TSMC’s new 3DFabric® technology services such as CoWoS® or or InFO for next generation HPC artificial intelligence (AI) and mobile applications The SoIC CoW Face-to-Back Gen-1 process is in production and the SoIC CoW Face-to-Back Gen-2 process with significant thermal performance improvement was qualified and started production in 2024 The SoIC CoW Face-to-Face Gen-1 process is under qualification and will provide an ultrahigh density connection solution Gen-2 process with advanced SoC (N2 and beyond) compatibility is under development and and will provide better band width and power performance gain The first-generation Compact Universal Photonics Engine (COUPE) with electrical chip on on photonics chip using SoIC bond has progressed well TSMC will continue to pursue SoIC technological improvements and co-optimize with the Company’s advanced silicon technologies for further gains in in transistor density system PPA (power performance and and area) and and cost ● CoWoS® As the leading 2 5D advanced packaging technology CoWoS® advanced packaging service is experiencing strong growth momentum due to the surging AI demand since 2023 The CoWoS®-S Si interposer technology has advanced from 1 1 0-reticle to 3 3 3-reticle size size (1 reticle reticle reticle size size is approximately 830mm2) during the past decade The development focus is now shifted to CoWoS®-L with reconstituted interposer of multiple local silicon interconnects (LSIs) The first CoWoS®-L at 3 5-reticle size has been developed and entered production in in 2024 New CoWoS®-L development targeting 5 5 5-reticle size interposer has been launched this year to meet higher performance goal in a a a a a a a package In parallel CoWoS® Co-packaged optics (CPO) for ultra-high-end network switch
is under development to integrate interposer-based CoW module and COUPE-based optical IO’s in one package to achieve higher data bandwidth and and to reduce system power consumption ● InFO In 2024 TSMC continued its industry leadership in in in high-volume manufacturing of InFO_PoP packaging for mobile applications The new feature with backside RDL was also qualified and ready for volume production ● Advanced Interconnect
With the growing demand for for high performance and and low power consumption products TSMC’s continuous innovations on on back-end-of-line interconnect provide its customers with competitive solutions In 2024 the Company developed a a novel interconnect structure that delivers power reduction
as as well as as improvements in in speed and routing density Furthermore the the research on on advanced materials demonstrated significant capacitance reduction
with robust reliability Those innovations will allow TSMC to continue scale interconnect for future generations of technology Corporate Research
TSMC corporate research stayed at at the forefront of low-dimensional transistor exploration with innovation in devices and and materials to drive higher performance and and lower power consumption to enable extremely scaled logic transistors At the 2024 Symposium on VLSI Technology
and Circuits (VLSI Symposium) TSMC demonstrated a a a a high performance nanosheet transistor with dense
aligned one-dimensional carbon nanotube channel With simultaneously improved gate control channel transconductance (gm) and contact resistance (Rc) this work demonstrated the highest performing 1-D carbon nanotube transistor (CNFET) From a a a process integration perspective at at the 2024 IEEE International Electron Devices Meeting (IEDM) TSMC presented the first electrical demonstration of a a a a a two-stacked nanosheet (NS) FET with a a a a a monolayer MoS2 channel utilizing a a a a a typical nanosheet release process prior to high-K metal gate deposition For potential applications in in 3-D integration with CMOS technology TSMC continued its extensive research on on back-end-of-line (BEOL) compatible oxide semiconductor field-effect transistors (OSFET) At the 2024 VLSI Symposium TSMC presented a a high-quality SnO oxide semiconductor channel that demonstrated the first successful sub-100nm channel length p-type SnO OSFET with ion current density 10~20 μA/μm and Ion/Ioff ratio over 104 Also at at the 2024 IEDM TSMC reported a n-type OSFET with W-doped In2O3 (IWO) channel using atomic layer deposition (ALD) An oxide capping capping layer and post-capping anneal were used to demonstrate an an enhancement-mode ALD IWO OSFET