Page 78 - 2017 TSMC Annual Report

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5nm full development focusing on manufacturing baseline process setup yield learning transistor and interconnect R/C performance improvement and reliability evaluation targeting risk production in 2019 ● Lithography Technology
The main focus for R&D lithography in in 2017 is 7nm technology transfer 5nm technology development and preparation
of 5nm beyond development development For 7nm development development the technology was smoothly transferred and R&D is working with the the fab to clean up the the remaining patterning issues As for 5nm development EUV (extreme ultraviolet) lithography showed promising imaging capability with expected good wafer yield R&D is working on on on EUV cost reduction reduction mask defect reduction reduction in in scanner and mask-making capability improvement In 2018 TSMC will intensively focus on improving EUV quality and adopting more EUV layers in in 5nm and beyond technology In 2017 the EUV program made continuous improvement in in light-source power and its stability which has enabled faster learning rate and process development for advanced nodes Additional progress was made with resist process pellicle and related mask blanks as as EUV technology moves closer to full scale R&D and manufacturing readiness ● Mask Technology
Mask technology is an an integral part of advanced lithography In 2017 R&D successfully implemented EUV mask technology into 7nm and 5nm nodes Solid progress was made on the production yield and the reduction of blank native defects to meet high-volume manufacturing requirements Integrated Interconnect and Packaging
Wafer Level System Integration (WLSI) is is a a a disruptive technology that leverages TSMC’s core competency in wafer processes and capacity in in building up heterogeneous system integration and packaging to to meet specific customer needs
in system-level performance power profile cycle time
and and cost WLSI and and its associated technology platforms including CoWoS® InFO and Under-Bump-Metallurgy Free Integration (UFI) are continuously evolving to fulfill diversified customer needs
in in mobile computing IoT automotive and high-performance computing ● 3D IC and Si Interposer
Interposer
CoWoS® demand is growing rapidly in in the high-performance computing (HPC) area both in in volume and the number of products Typical CoWoS® applications involve
heterogeneous integration of a a a a large logic chip at at 16/12/7nm and a a a growing number of HBM2 (second generation high bandwidth memory) stacks Consequently the Si interposer area has grown very fast to to an astonishing ~1400mm2 in in some applications TSMC continues to provide a a a complete Si-to-package business model for CoWoS® manufacturing ● Advanced Fan-Out Packaging
In 2017 TSMC continued to lead in in high-volume manufacturing (HVM) of InFO-PoP Gen-2 packaging for mobile applications processors During the the year the the Company also successfully qualified InFO-PoP Gen-3 advanced packaging technology for mobile applications and started risk production in Integrated Fan-Out on Substrate (InFO-oS) for HPC die-partition application The newly developed InFO-PoP could be stacked with with versatile commercial DRAM with with competitive performance This InFO-PoP with backside RDL will boost penetration into mobile application application processor application application with wide coverage from premium to mid and low tiers TSMC has scheduled HVM readiness by end of 2018 To meet demand with the coming of 5G mobile communications TSMC has developed an an an advanced InFO InFO antenna in package (InFO-AIP) technology in which the RF chip and millimeter-wave antenna are integrated into an InFO InFO package InFO-AIP technology provides high-performance low-power small-size low-cost solutions for millimeter wave system applications such as 5G mobile video streaming and virtual reality (VR) wireless communications This technology can also support the fast-evolving applications in in in in car radar auto-driving and driving driving safety ● Advanced Interconnect TSMC has made significant progress in in innovative materials and processes for continuous interconnect scaling The Company has developed and verified a a a novel low-k process using selective deposition on on dielectric which can lower capacitance loading improve electric performance and enhance device reliability In addition TSMC has developed a a a a a a new barrier and copper gap filling process to further extend copper material applications and and provide competitive wire conductance and and via resistance for advanced technology nodes Verification of these new materials and processes is progressing well for beyond 5nm technologies Advanced Transistor Research
Innovation in in transistor architectures and materials continues to enable higher speed and reduced power consumption
in advanced logic technologies TSMC is at the forefront of