Beijing2019/10/29
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Nurture Innovation through OIP Collaboration

  • Discover technologies and joint design solutions for HPC, Mobile, Automotive and IoT.
  • Hear directly from 30 technical papers and over 70 ecosystem companies' showcase.
  • Network with more than 1,000 industry experts and end users
REGISTER NOW – Beijing VIEW AGENDA 2018 HIGHLIGHTS

Join the Premier Semiconductor Conference

  • Emerging advanced node design challenges including 5nm, 6nm, 7nm, 12FFC/16FFC, 16FF+, 22ULP/ULL, 28nm, and ultra-low power process technologies.
  • Updated design solutions for specialty technologies supporting Internet-of-Thing (IoT) applications
  • Successful, real-life applications of design technologies and IP from ecosystem members and TSMC customers
  • Ecosystem-specific TSMC reference flow implementations
  • New innovations for next generation product designs targeting HPC, mobile, automotive and IoT applications

Featured Speakers

Dr. Cliff Hou
Vice President, Research & Development / Technology Development, TSMC
Mr. Roger Luo
President of TSMC Nanjing

Agenda

Beijing

October 29 (Tuesday)
Plenary Session
08:30 – 09:30 (10 min) Registration Opens & Ecosystem Pavilion
09:30 – 09:50 (40 min) Welcome Remarks
09:50 – 10:40 (20 min) TSMC and its Ecosystem for Innovation
10:40 – 11:00 (20 min) Coffee Break & Ecosystem Pavilion

 

Technical Session
  EDA Track IP & Design Services Track
11:00 – 11:30 TSMC 3DIC & RF Design Enablement Updates
TSMC		 TSMC EDA & IP Design Enablement Updates
TSMC
11:30 – 12:00(20 min) High-Performance AI Chip Implementation with Fusion Technologies on tsmc Advance Node
Cambricon / Synopsys		 The Challenges Posed by Dynamic Uncertainty on AI & ML Devices Targeting 16nm, 7nm & 5nm
Moortec Semiconductor Ltd
12:00 – 13:00 Lunch & Ecosystem Pavilion
13:00 – 13:30 Maximize TOPS (Tera Operations Per Second) per Watt for AI Chip using Early Power Analysis and Reduction
iluvatar coreX / ANSYS		 Enhanced OTP solutions in TSMC for IoT, Edge AI and Automotive Applications
eMemory Technology Inc.
13:30 – 14:00 Physical Design Methodologies for Next Generation Network Chips with TSMC 7nm Process Technology
ZTE Sanechips / Cadence Design Systems		 From Multicore to Manycore, Enabling RISC-V Toward High Performance Computing
Andes Technology
14:00 – 14:30 Comprehensive Chip Package System (CPS) Electrostatic Discharge (ESD) Simulation
UNISOC / ANSYS		 Simplify Energy Efficient designs with cost-effective SoC Platform
Dolphin Design
14:30 – 15:00 Empyrean ALPS GPU-Turbo Accelerates Analog Verification at TSMC Advanced Nodes
Empyrean Software		 Modular-ADC Based Smart Sensors
M31 Technology
15:00 – 15:30 Coffee Break & Partner Pavilion
15:30 – 16:00 Novel SIPI Approach for 2.5D&3DIC Application
ZTE Sanechips / ANSYS		 Advancing complex 4K and 8K digital television design with Arm POP IP on TSMC 22nm ULP
Novatek / Arm
16:00 – 16:30 Clock Distribution Strategies for Fast Timing Closure with TSMC 7nm Process
Cadence Design Systems / ZTE Sanechips		 How semiconductor IP is at the core of generating Autonomous vehicle value
Imagination Technologies
16:30 – 17:00 Power Analysis Challenges and solutions of PI sign-off for next generation large scale chips with TSMC 7nm process technology
ZTE Sanechips / ANSYS		 Chiplets solutions using CoWoS and InFO with 112Gbps Serdes and HBM2E/3.2Gbps for AI, HPC and Networking
Global Unichip Corporation
17:00 – 17:10 Lucky Draw

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